AN 916: JESD204C Intel® FPGA IP and ADI AD9081/AD9082 MxFE* Interoperability Report for Intel® Stratix® 10 E-Tile Devices

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ID 683157
Date 6/22/2020
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Document Table of Contents
Document Table of Contents x
1. JESD204C Intel® FPGA IP and ADI AD9081/AD9082 MxFE* Hardware Checkout Report for Intel® Stratix® 10 E-Tile Devices
1. JESD204C Intel® FPGA IP and ADI AD9081/AD9082 MxFE* Hardware Checkout Report for Intel® Stratix® 10 E-Tile Devices x
1.1. Hardware Requirements 1.2. Hardware Setup 1.3. JESD204C Intel® FPGA IP and ADC Hardware Checkout 1.4. JESD204C Intel® FPGA IP and DAC Hardware Checkout 1.5. Document Revision History for AN 916: JESD204C Intel® FPGA IP and ADI AD9081/AD9082 MxFE* Interoperability Report for Intel® Stratix® 10 E-Tile Devices 1.6. Appendix
1.3. JESD204C Intel® FPGA IP and ADC Hardware Checkout x
1.3.1. ADC Hardware Checkout Methodology 1.3.2. JESD204C Intel® FPGA IP and ADC Configurations 1.3.3. ADC Test Results 1.3.4. ADC Test Result Comment
1.3.1. ADC Hardware Checkout Methodology x
1.3.1.1. Receiver Data Link Layer 1.3.1.2. Receiver Transport Layer
1.3.1.1. Receiver Data Link Layer x
1.3.1.1.1. Sync Header Alignment 1.3.1.1.2. Extended Multiblock Alignment (EMBA)
1.4. JESD204C Intel® FPGA IP and DAC Hardware Checkout x
1.4.1. DAC Hardware Checkout Methodology 1.4.2. JESD204C Intel® FPGA IP and DAC Configurations 1.4.3. DAC Test Results 1.4.4. DAC Test Result Comment
1.4.1. DAC Hardware Checkout Methodology x
1.4.1.1. Transmitter Data Link Layer 1.4.1.2. Transmitter Transport Layer
1.4.1.1. Transmitter Data Link Layer x
1.4.1.1.1. TX_RST
1. JESD204C Intel® FPGA IP and ADI AD9081/AD9082 MxFE* Hardware Checkout Report for Intel® Stratix® 10 E-Tile Devices

1.3.1.1.1. Sync Header Alignment

Table 1.  SHA Test Cases
Test Case Objective Description Passing Criteria
SHA.1 Check if Sync Header Lock is asserted after the completion of reset sequence. The following signals in <ip_variant_name>_base.v are tapped:
  • j204c_rx_rst_n
  • j204c_rx_sh_lock
  • j204c_rx_int

The rxlink_clk is used as the sampling clock for the Signal Tap.

  • The j204c_rx_sh_lock is asserted after the deassertion of j204c_rx_rst_n.
  • The j204c_rx_int signal should stay low if there is no error.
SHA.2 Check Sync Header Lock status after sync header lock is achieved (or during the EMBA phase) and stable. The following signals in <ip_variant_name>_base.v are tapped:
  • j204c_rx_sh_lock
  • j204c_rx_int

The rxlink_clk is used as the sampling clock for the Signal Tap.

  • The j204c_rx_sh_lock should remain asserted. 1
  • The j204c_rx_int signal should stay low if there is no error. 2

1 The j204c_rx_sh_lock signal should remain asserted after 12 hours.
2 The j204c_rx_int signal should not be asserted after 12 hours.
Level Two Title