AN 916: JESD204C Intel® FPGA IP and ADI AD9081/AD9082 MxFE* Interoperability Report for Intel® Stratix® 10 E-Tile Devices

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ID 683157
Date 6/22/2020
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Document Table of Contents
Document Table of Contents x
1. JESD204C Intel® FPGA IP and ADI AD9081/AD9082 MxFE* Hardware Checkout Report for Intel® Stratix® 10 E-Tile Devices
1. JESD204C Intel® FPGA IP and ADI AD9081/AD9082 MxFE* Hardware Checkout Report for Intel® Stratix® 10 E-Tile Devices x
1.1. Hardware Requirements 1.2. Hardware Setup 1.3. JESD204C Intel® FPGA IP and ADC Hardware Checkout 1.4. JESD204C Intel® FPGA IP and DAC Hardware Checkout 1.5. Document Revision History for AN 916: JESD204C Intel® FPGA IP and ADI AD9081/AD9082 MxFE* Interoperability Report for Intel® Stratix® 10 E-Tile Devices 1.6. Appendix
1.3. JESD204C Intel® FPGA IP and ADC Hardware Checkout x
1.3.1. ADC Hardware Checkout Methodology 1.3.2. JESD204C Intel® FPGA IP and ADC Configurations 1.3.3. ADC Test Results 1.3.4. ADC Test Result Comment
1.3.1. ADC Hardware Checkout Methodology x
1.3.1.1. Receiver Data Link Layer 1.3.1.2. Receiver Transport Layer
1.3.1.1. Receiver Data Link Layer x
1.3.1.1.1. Sync Header Alignment 1.3.1.1.2. Extended Multiblock Alignment (EMBA)
1.4. JESD204C Intel® FPGA IP and DAC Hardware Checkout x
1.4.1. DAC Hardware Checkout Methodology 1.4.2. JESD204C Intel® FPGA IP and DAC Configurations 1.4.3. DAC Test Results 1.4.4. DAC Test Result Comment
1.4.1. DAC Hardware Checkout Methodology x
1.4.1.1. Transmitter Data Link Layer 1.4.1.2. Transmitter Transport Layer
1.4.1.1. Transmitter Data Link Layer x
1.4.1.1.1. TX_RST
1. JESD204C Intel® FPGA IP and ADI AD9081/AD9082 MxFE* Hardware Checkout Report for Intel® Stratix® 10 E-Tile Devices

1.3.2. JESD204C Intel® FPGA IP and ADC Configurations

The JESD204C Intel® FPGA IP parameters (L, M, and F) in this hardware checkout are natively supported by the AD9081 device configuration registers. The transceiver data rate, sampling clock frequency, and other JESD204C parameters comply with the AD9081 operating conditions.

The hardware checkout testing implements the JESD204C Intel® FPGA IP with the following parameter configurations.

Global setting for below configuration:
  • E = 1
  • CF = 0
  • FCLK_MULP = 2
  • WIDTH_MULP = 4
  • Subclass = 0
  • SH_CONFIG = CRC-12
  • FPGA Management Clock (MHz) = 100
Table 4.  Parameter Configuration
Mode LMF N/N’ S E Decimation Mode ADC Rate (Msps) Data Rate (Msps)8 Lane Rate (Mbps)9 FPGA Device Clock (MHz) 10 FPGA Link Clock (MHz) 11 FPGA Frame Clock (MHz)11 Data Pattern
1 882 16 1 1 2x1 3000 1500 24750 375 187.5 375 Ramp
8 Data rate = ADC rate x decimation factor.
9 Lane rate = (M/L) x N' x (66/64) x data rate.
10 The FPGA device clock is used to clock the core PLL and the transceiver.
11 The link clock and the frame clock are derived from the device clock using the core PLL.
Level Two Title