AN 584: Timing Closure Methodology for Advanced FPGA Designs

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ID 683145
Date 10/08/2021
Public
Document Table of Contents
Document Table of Contents x
1. AN 584: Timing Closure Methodology for Advanced FPGA Designs
1. AN 584: Timing Closure Methodology for Advanced FPGA Designs x
1.1. Plan Early for Timing Closure 1.2. Customize Settings Per Application 1.3. Change Fitter Placement Seeds 1.4. Planning for Timing Closure 1.5. Best Practices for Timing Closure 1.6. Resolving Common Timing Issues 1.7. Conclusion 1.8. Document Revision History for AN 584: Timing Closure Methodology for Advanced FPGA Designs
1.4. Planning for Timing Closure x
1.4.1. Timing Closure Planning at Specification Stage 1.4.2. Timing Closure Planning at Coding and Compilation Stage
1.4.1. Timing Closure Planning at Specification Stage x
1.4.1.1. Plan for the Target FPGA Device 1.4.1.2. Plan for On-Chip Debugging
1.4.2. Timing Closure Planning at Coding and Compilation Stage x
1.4.2.1. Plan for Design Hierarchy and Block Partitioning 1.4.2.2. Plan for Early Compilation of Design Blocks 1.4.2.3. Plan for Verification
1.5. Best Practices for Timing Closure x
1.5.1. Performance Planning General Guidelines 1.5.2. Follow Synchronous Design Practices 1.5.3. Follow Recommended Coding Styles 1.5.4. Constraining and Compiling Your Design
1.5.4. Constraining and Compiling Your Design x
1.5.4.1. Setting Location Constraints 1.5.4.2. Setting Proper Timing Constraints 1.5.4.3. Using Optimal Compiler Settings for Your Design
1.6. Resolving Common Timing Issues x
1.6.1. Excessive Logic Levels 1.6.2. Improper Timing Constraints 1.6.3. Handling High Fan-Out Registers 1.6.4. Metastability Issues 1.6.5. Reset Signal Related Issues 1.6.6. Small Margin Timing Constraint Failures 1.6.7. Long Compilation Times
1.6.2. Improper Timing Constraints x
1.6.2.1. Check Constraint Diagnostics
1.6.4. Metastability Issues x
1.6.4.1. Check CDC Design Assistant Rule Violations 1.6.4.2. Check CDC Report
1.6.5. Reset Signal Related Issues x
1.6.5.1. Recovery and Removal Issues
1. AN 584: Timing Closure Methodology for Advanced FPGA Designs

1.5.4.3. Using Optimal Compiler Settings for Your Design

In addition to using the correct design methodology and proper timing constraints, use the optimal Compiler settings for your design goals.

The Intel® Quartus® Prime software offers many settings to help you meet different design requirements. If you do not specify the appropriate setting, design performance may suffer.

The Intel® Quartus® Prime software has various settings to help meet different design requirements. For example, if your design targets a mobile device, you might specify the Aggressive power setting to optimize your design for lowest power consumption. Similarly, if your design targets a low-cost system, you might pick a device with a specific architecture and optimize your design for that architecture. If you want to reduce the size of the design, you can optimize for Aggressive area.

The Compiler's default Optimization Mode settings offer a balance of performance, area, routability, power, and compilation time. By trading off one optimization for another, you can meet your preferred design requirements.

Select the Optimization Mode in Assignments > Settings > Compiler Settings > Optimization Mode.

Figure 3. Compiler Optimization Modes

There is no single collection of settings that achieves the best performance for all designs. Each design is unique, and a setting set that derives the best performance for one design has a different impact in another design.

Specifying the Superior performance optimization modes can help in some designs, but some of the modes can have a detrimental impact on your primary goal. You might be making optimizations that increase the compilation time without a corresponding improvement in performance. Only apply settings that help meet your design goals.

The settings that you specify for a project revision are specific to that revision. When you make substantial changes to a design, you may need to modify some of the Compiler settings. Whenever you make large changes in your design, you can use the Design Space Explorer II (DSE) to run seed sweeps that identify the best collections of settings for your revision. You can do multiple DSE runs with different compile settings and using multiple seeds by clicking Tools > Launch Design Space Explorer II.

Figure 4. Design Space Explorer II Exploration Options
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