AN 584: Timing Closure Methodology for Advanced FPGA Designs

Download PDF
ID 683145
Date 10/08/2021
Public
Document Table of Contents
Document Table of Contents x
1. AN 584: Timing Closure Methodology for Advanced FPGA Designs
1. AN 584: Timing Closure Methodology for Advanced FPGA Designs x
1.1. Plan Early for Timing Closure 1.2. Customize Settings Per Application 1.3. Change Fitter Placement Seeds 1.4. Planning for Timing Closure 1.5. Best Practices for Timing Closure 1.6. Resolving Common Timing Issues 1.7. Conclusion 1.8. Document Revision History for AN 584: Timing Closure Methodology for Advanced FPGA Designs
1.4. Planning for Timing Closure x
1.4.1. Timing Closure Planning at Specification Stage 1.4.2. Timing Closure Planning at Coding and Compilation Stage
1.4.1. Timing Closure Planning at Specification Stage x
1.4.1.1. Plan for the Target FPGA Device 1.4.1.2. Plan for On-Chip Debugging
1.4.2. Timing Closure Planning at Coding and Compilation Stage x
1.4.2.1. Plan for Design Hierarchy and Block Partitioning 1.4.2.2. Plan for Early Compilation of Design Blocks 1.4.2.3. Plan for Verification
1.5. Best Practices for Timing Closure x
1.5.1. Performance Planning General Guidelines 1.5.2. Follow Synchronous Design Practices 1.5.3. Follow Recommended Coding Styles 1.5.4. Constraining and Compiling Your Design
1.5.4. Constraining and Compiling Your Design x
1.5.4.1. Setting Location Constraints 1.5.4.2. Setting Proper Timing Constraints 1.5.4.3. Using Optimal Compiler Settings for Your Design
1.6. Resolving Common Timing Issues x
1.6.1. Excessive Logic Levels 1.6.2. Improper Timing Constraints 1.6.3. Handling High Fan-Out Registers 1.6.4. Metastability Issues 1.6.5. Reset Signal Related Issues 1.6.6. Small Margin Timing Constraint Failures 1.6.7. Long Compilation Times
1.6.2. Improper Timing Constraints x
1.6.2.1. Check Constraint Diagnostics
1.6.4. Metastability Issues x
1.6.4.1. Check CDC Design Assistant Rule Violations 1.6.4.2. Check CDC Report
1.6.5. Reset Signal Related Issues x
1.6.5.1. Recovery and Removal Issues
1. AN 584: Timing Closure Methodology for Advanced FPGA Designs

1.4.2.2. Plan for Early Compilation of Design Blocks

After first identifying the major functional blocks of the design, you can partition the design into manageable blocks to facilitate multiple designers and independent and incremental optimization of design blocks.

Compile the major blocks in your design as soon as you can, even if your design is not complete. By doing this, you can also identify resource issues early in the design cycle.

A common reason for prolonged design cycles is waiting for all code completion before compiling the design. With this approach, you do not detect significant issues until the design and dependencies are very mature.

Using the incremental block-cased compilation flow, you can assign blocks that are not yet available, or that are being developed independently as "empty" partitions.

When creating design partitions:

  • Try to minimize inter-block connections.
  • Register all inputs and outputs from each block to avoid critical timing paths crossing between partition boundaries.
  • Details of other partitions contents are not visible to the Compiler when compiling a single partition block. Therefore, optimization (or logic minimization) across partitions cannot occur.
  • Add each major block or partition in your design as soon as HDL coding is completed and compile incrementally.
  • If certain block partitions are finished and no modification is needed, you have the option to preserve these partitions as soon as they meet timing requirements.

Incremental timing closure can help your design meet timing faster, as the Fitter works more on optimizations and small RTL changes without influencing any preserved partitions.

Compiling blocks early using the incremental block-based compilation helps you to uncover and resolve design issues early before they can become complicated problems in the final timing closure stages.

You can set the following options to reduce the total compile time during the initial stages of your design. These options are especially helpful for large or complex blocks that you want to initially compile independently, or when ready to start integrating the block:

Click Assignments > Settings > Compiler Settings > Optimization Mode > Compile Time, and then choose one of the following:

  • Aggressive Compile Time
  • Fast Functional Test

Both of these modes perform initial timing and functional analyses without requiring excessive compile time.

Figure 2. Compile Time Optimization Mode Settings

For more information about incremental block-based compilation, refer to Incremental Block-Based Compilation Flow and Setting-Up Team-Based Designs sections of the Intel® Quartus® Prime Pro Edition User Guide: Block-Based Design.

Related Information
Level Two Title