AN 584: Timing Closure Methodology for Advanced FPGA Designs

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ID 683145
Date 10/08/2021
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Document Table of Contents
Document Table of Contents x
1. AN 584: Timing Closure Methodology for Advanced FPGA Designs
1. AN 584: Timing Closure Methodology for Advanced FPGA Designs x
1.1. Plan Early for Timing Closure 1.2. Customize Settings Per Application 1.3. Change Fitter Placement Seeds 1.4. Planning for Timing Closure 1.5. Best Practices for Timing Closure 1.6. Resolving Common Timing Issues 1.7. Conclusion 1.8. Document Revision History for AN 584: Timing Closure Methodology for Advanced FPGA Designs
1.4. Planning for Timing Closure x
1.4.1. Timing Closure Planning at Specification Stage 1.4.2. Timing Closure Planning at Coding and Compilation Stage
1.4.1. Timing Closure Planning at Specification Stage x
1.4.1.1. Plan for the Target FPGA Device 1.4.1.2. Plan for On-Chip Debugging
1.4.2. Timing Closure Planning at Coding and Compilation Stage x
1.4.2.1. Plan for Design Hierarchy and Block Partitioning 1.4.2.2. Plan for Early Compilation of Design Blocks 1.4.2.3. Plan for Verification
1.5. Best Practices for Timing Closure x
1.5.1. Performance Planning General Guidelines 1.5.2. Follow Synchronous Design Practices 1.5.3. Follow Recommended Coding Styles 1.5.4. Constraining and Compiling Your Design
1.5.4. Constraining and Compiling Your Design x
1.5.4.1. Setting Location Constraints 1.5.4.2. Setting Proper Timing Constraints 1.5.4.3. Using Optimal Compiler Settings for Your Design
1.6. Resolving Common Timing Issues x
1.6.1. Excessive Logic Levels 1.6.2. Improper Timing Constraints 1.6.3. Handling High Fan-Out Registers 1.6.4. Metastability Issues 1.6.5. Reset Signal Related Issues 1.6.6. Small Margin Timing Constraint Failures 1.6.7. Long Compilation Times
1.6.2. Improper Timing Constraints x
1.6.2.1. Check Constraint Diagnostics
1.6.4. Metastability Issues x
1.6.4.1. Check CDC Design Assistant Rule Violations 1.6.4.2. Check CDC Report
1.6.5. Reset Signal Related Issues x
1.6.5.1. Recovery and Removal Issues
1. AN 584: Timing Closure Methodology for Advanced FPGA Designs

1.3. Change Fitter Placement Seeds

The Intel® Quartus® Prime Compiler's Fitter stage performs the place and route of your design. When run, the Fitter creates a semi-random initial placement for the logic it derives from the initial condition of your design RTL. The Fitter's goal is to find a placement that the Compiler can successfully route and that also meets all constraints that you specify.

It is possible to achieve a successful place and route using different initial placements. The Fitter searches for the best solution among a set of different possible and valid solutions within the solution space. The Fitter might converge to different solutions in the solution space, depending on the given initial conditions.

The initial condition of the design is a function of all the source files, optimization settings, and the Fitter Initial Placement Seed setting value. A change in any of these variables results in a change in the initial placement. A change in initial placement affects how optimizations proceed, producing a different Fitter result. This variation in Fitter results is the “Fitter seed effect.”

The Fitter seed effect determines which optimizations happen during a Fitter run. Because the project seed consists of inputs you specify in the Intel® Quartus® Prime software, any modification, such as changing a net name, pin name, or making a new assignment, changes the project seed and the final results.

A new Fitter run with a different seed places the Fitter into a new area in the solution space, resulting in a different initial placement. If you change the Fitter seed, the Compiler might converge on a different solution because of the modified initial placements. Therefore, changing the Fitter seed can produce different place and route results.

You specify a non-negative integer as an input to the Fitter seed. Changing the Fitter seed value may not produce a better fit, but the change does make the Fitter use a different initial placement. This integer seed value allows you to try different initial placements without any change in the design or settings.

You can run a “seed sweep” to try different initial placements to guide a Fitter, using different seeds or settings to find the best performance results for a given design using the same optimization settings.

You can use a seed sweep to determine the optimal seed value for your design if other initial conditions remain unchanged. The default Fitter Initial Placement Seed value is 1. To change the default Fitter Initial Placement Seed value:

  1. Click Assignments > Settings > Compiler Settings.
  2. On the Optimization Mode tab, click the Advance Settings (Fitter) button.
  3. In the search field, type seed.
  4. For Fitter Initial Placement Seed, specify a new non-negative integer value.
Figure 1.  Fitter Initial Placement Seed

As an alternative to the GUI setting, you can specify the following equivalent setting in the .qsf file: 

set_global_assignment -name SEED <value>

Using different seed values causes a variance in the Fitter optimization results for compilations on the same design. For example, a seed value of 2 might have the best results for one of your designs, but when you make other changes in the design, either in the source or in the settings, that value might not produce the best results. Also, in a different design, a seed value of 1 might give the best results. On average, you can expect to see about ±5% variance in the results across different seed values.

There is no definitive seed value that guarantees the best results for every design. The varying results with seed value changes are design dependent.

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