AN 584: Timing Closure Methodology for Advanced FPGA Designs

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ID 683145
Date 10/08/2021
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Document Table of Contents
Document Table of Contents x
1. AN 584: Timing Closure Methodology for Advanced FPGA Designs
1. AN 584: Timing Closure Methodology for Advanced FPGA Designs x
1.1. Plan Early for Timing Closure 1.2. Customize Settings Per Application 1.3. Change Fitter Placement Seeds 1.4. Planning for Timing Closure 1.5. Best Practices for Timing Closure 1.6. Resolving Common Timing Issues 1.7. Conclusion 1.8. Document Revision History for AN 584: Timing Closure Methodology for Advanced FPGA Designs
1.4. Planning for Timing Closure x
1.4.1. Timing Closure Planning at Specification Stage 1.4.2. Timing Closure Planning at Coding and Compilation Stage
1.4.1. Timing Closure Planning at Specification Stage x
1.4.1.1. Plan for the Target FPGA Device 1.4.1.2. Plan for On-Chip Debugging
1.4.2. Timing Closure Planning at Coding and Compilation Stage x
1.4.2.1. Plan for Design Hierarchy and Block Partitioning 1.4.2.2. Plan for Early Compilation of Design Blocks 1.4.2.3. Plan for Verification
1.5. Best Practices for Timing Closure x
1.5.1. Performance Planning General Guidelines 1.5.2. Follow Synchronous Design Practices 1.5.3. Follow Recommended Coding Styles 1.5.4. Constraining and Compiling Your Design
1.5.4. Constraining and Compiling Your Design x
1.5.4.1. Setting Location Constraints 1.5.4.2. Setting Proper Timing Constraints 1.5.4.3. Using Optimal Compiler Settings for Your Design
1.6. Resolving Common Timing Issues x
1.6.1. Excessive Logic Levels 1.6.2. Improper Timing Constraints 1.6.3. Handling High Fan-Out Registers 1.6.4. Metastability Issues 1.6.5. Reset Signal Related Issues 1.6.6. Small Margin Timing Constraint Failures 1.6.7. Long Compilation Times
1.6.2. Improper Timing Constraints x
1.6.2.1. Check Constraint Diagnostics
1.6.4. Metastability Issues x
1.6.4.1. Check CDC Design Assistant Rule Violations 1.6.4.2. Check CDC Report
1.6.5. Reset Signal Related Issues x
1.6.5.1. Recovery and Removal Issues
1. AN 584: Timing Closure Methodology for Advanced FPGA Designs

1.6.4. Metastability Issues

Clock-domain-crossing (CDC) signals can cause metastability on the capturing clock domain register. To reduce the possibility of going metastable, you must synchronize all signals between asynchronous clock domains with multiple stages of synchronizing registers.

Signals with a source in one clock domain may be registered in another clock domain, causing the data input to fail the setup or hold time requirements of the destination register. This may cause the output of the latching register to go to an intermediate state between a logical 1 and a logical 0. Although this intermediate value eventually resolves to a ‘1’ or ‘0,’ the issue is the indeterminate time the value takes to resolve itself.

Generally, a minimum of two stages is recommended. The Intel® Quartus® Prime software by default is set to look for three register stages to place as close together to obtain better Mean Time Between Failures (MTBF).

To change this default value, click Assignments > Settings > Compiler Settings > Optimization Mode > Advanced Settings (Synthesis) and specify a value for Synchronization Register Chain Length.

Figure 9. Setting Synchronization Register Chain Length

The Intel® Quartus® Prime software can analyze designs for metastability, and offers recommendations to reduce metastability. You can compute MTBF on circuit parameters. You should increase the MTBF as much as possible.

Isolating failures caused by metastability can be problematic because they can appear as sporadic device failures, which are hard to debug. Increasing the MTBF might reduce the occurrence of such failures.

Metastability problems in your design can appear as incorrectly operating state machines. Symptoms include skipped states, or state machines that do not recover from a stage or lock-up. State machines might also miss triggering events that cause state transitions. Such problems might occur when you do not synchronize control signals to a state machine coming from other clock domains.

By synchronizing all asynchronous control signals, you can ensure that these signals remain stable for an integral number of clock cycles, and trigger transitions appropriately.

For more information about metastability, refer to the Managing Metastability in Intel® Quartus® Prime Pro Edition User Guide: Design Recommendations.


Section Content
Check CDC Design Assistant Rule Violations
Check CDC Report

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