AN 584: Timing Closure Methodology for Advanced FPGA Designs

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ID 683145
Date 10/08/2021
Public
Document Table of Contents
Document Table of Contents x
1. AN 584: Timing Closure Methodology for Advanced FPGA Designs
1. AN 584: Timing Closure Methodology for Advanced FPGA Designs x
1.1. Plan Early for Timing Closure 1.2. Customize Settings Per Application 1.3. Change Fitter Placement Seeds 1.4. Planning for Timing Closure 1.5. Best Practices for Timing Closure 1.6. Resolving Common Timing Issues 1.7. Conclusion 1.8. Document Revision History for AN 584: Timing Closure Methodology for Advanced FPGA Designs
1.4. Planning for Timing Closure x
1.4.1. Timing Closure Planning at Specification Stage 1.4.2. Timing Closure Planning at Coding and Compilation Stage
1.4.1. Timing Closure Planning at Specification Stage x
1.4.1.1. Plan for the Target FPGA Device 1.4.1.2. Plan for On-Chip Debugging
1.4.2. Timing Closure Planning at Coding and Compilation Stage x
1.4.2.1. Plan for Design Hierarchy and Block Partitioning 1.4.2.2. Plan for Early Compilation of Design Blocks 1.4.2.3. Plan for Verification
1.5. Best Practices for Timing Closure x
1.5.1. Performance Planning General Guidelines 1.5.2. Follow Synchronous Design Practices 1.5.3. Follow Recommended Coding Styles 1.5.4. Constraining and Compiling Your Design
1.5.4. Constraining and Compiling Your Design x
1.5.4.1. Setting Location Constraints 1.5.4.2. Setting Proper Timing Constraints 1.5.4.3. Using Optimal Compiler Settings for Your Design
1.6. Resolving Common Timing Issues x
1.6.1. Excessive Logic Levels 1.6.2. Improper Timing Constraints 1.6.3. Handling High Fan-Out Registers 1.6.4. Metastability Issues 1.6.5. Reset Signal Related Issues 1.6.6. Small Margin Timing Constraint Failures 1.6.7. Long Compilation Times
1.6.2. Improper Timing Constraints x
1.6.2.1. Check Constraint Diagnostics
1.6.4. Metastability Issues x
1.6.4.1. Check CDC Design Assistant Rule Violations 1.6.4.2. Check CDC Report
1.6.5. Reset Signal Related Issues x
1.6.5.1. Recovery and Removal Issues
1. AN 584: Timing Closure Methodology for Advanced FPGA Designs

1.6.5.1. Recovery and Removal Issues

The Timing Analyzer performs recovery and removal analysis in addition to setup and hold analysis. Providing an appropriate reset structure for your design helps the Fitter to place logic to meet recovery and removal timing requirements.

Recovery time is analogous to setup time, and removal time is analogous to hold time. The difference between these sets of timing parameters is that recovery and removal analysis occurs for asynchronous signals (such as reset) with respect to the clock. Recovery and removal analysis helps you to ensure that your synchronous logic behaves correctly when you assert and deassert an asynchronous control signal.

A problem that can occur with a reset signal that spans across the device, is that the signal may not arrive at the same time relative to the clock edge for all the device registers.

When such a reset signal is deasserted, all of the registers should exit reset. However, if the reset signal does not meet the recovery time for some registers in the design, those registers may not exit reset until after the next clock edge.

If such registers do not all come out of reset in the same clock cycle, and if there are state machines with important transitions after this clock cycle, these state machines may not behave as you expect. This condition can cause a design failure. Similarly, a removal error can occur if you remove the reset too early, relative to the clock, and some registers exit reset one cycle earlier.

Using a VDD-based reset synchronizer, and adding another register at the end for duplication to drive different block resets, helps the Fitter to manage the placements to meet these timing requirements.

For more information on resets, refer to AN 917: Reset Design Techniques for Intel Hyperflex Architecture FPGAs.

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