AN 584: Timing Closure Methodology for Advanced FPGA Designs

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ID 683145
Date 10/08/2021
Public
Document Table of Contents
Document Table of Contents x
1. AN 584: Timing Closure Methodology for Advanced FPGA Designs
1. AN 584: Timing Closure Methodology for Advanced FPGA Designs x
1.1. Plan Early for Timing Closure 1.2. Customize Settings Per Application 1.3. Change Fitter Placement Seeds 1.4. Planning for Timing Closure 1.5. Best Practices for Timing Closure 1.6. Resolving Common Timing Issues 1.7. Conclusion 1.8. Document Revision History for AN 584: Timing Closure Methodology for Advanced FPGA Designs
1.4. Planning for Timing Closure x
1.4.1. Timing Closure Planning at Specification Stage 1.4.2. Timing Closure Planning at Coding and Compilation Stage
1.4.1. Timing Closure Planning at Specification Stage x
1.4.1.1. Plan for the Target FPGA Device 1.4.1.2. Plan for On-Chip Debugging
1.4.2. Timing Closure Planning at Coding and Compilation Stage x
1.4.2.1. Plan for Design Hierarchy and Block Partitioning 1.4.2.2. Plan for Early Compilation of Design Blocks 1.4.2.3. Plan for Verification
1.5. Best Practices for Timing Closure x
1.5.1. Performance Planning General Guidelines 1.5.2. Follow Synchronous Design Practices 1.5.3. Follow Recommended Coding Styles 1.5.4. Constraining and Compiling Your Design
1.5.4. Constraining and Compiling Your Design x
1.5.4.1. Setting Location Constraints 1.5.4.2. Setting Proper Timing Constraints 1.5.4.3. Using Optimal Compiler Settings for Your Design
1.6. Resolving Common Timing Issues x
1.6.1. Excessive Logic Levels 1.6.2. Improper Timing Constraints 1.6.3. Handling High Fan-Out Registers 1.6.4. Metastability Issues 1.6.5. Reset Signal Related Issues 1.6.6. Small Margin Timing Constraint Failures 1.6.7. Long Compilation Times
1.6.2. Improper Timing Constraints x
1.6.2.1. Check Constraint Diagnostics
1.6.4. Metastability Issues x
1.6.4.1. Check CDC Design Assistant Rule Violations 1.6.4.2. Check CDC Report
1.6.5. Reset Signal Related Issues x
1.6.5.1. Recovery and Removal Issues
1. AN 584: Timing Closure Methodology for Advanced FPGA Designs

1.6.6. Small Margin Timing Constraint Failures

If your design fails to meet timing requirements by a small margin, you can use DSE II to help you select the optimum project settings to meet timing. DSE II runs multiple compilations and compares the results to determine the best combination of settings. Using DSE II to run a seed sweep also helps you compensate for the seed effect, as Change Fitter Placement Seeds describes.

If you make changes to your RTL code or project settings, run a DSE II seed sweep to ensure that the RTL or settings changes are the true cause of improvements, rather than the seed effect.

If your design still fails to meet timing by a small margin, you can use the best performing seed to lock down the placement of clocks, RAMs, and DSPs from that compilation. You lock these placements through assignment back-annotation, and then run another round of seed-sweep using the locked-down placements. The subsequent compilations can benefit from the initial, desired placement settings of the previous best performing seed.

To lock down placement through assignment back-annotation, click Assignments > Back-Annotate Assignments, and then select the types of assignments to back-annotate. You can choose to append the back-annotated assignments to the .qsf, or to create a Tcl file of assignments that you can source to the .qsf.

Figure 12. Back-Annotate Assignments Dialog Box
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