AN 584: Timing Closure Methodology for Advanced FPGA Designs

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ID 683145
Date 10/08/2021
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Document Table of Contents
Document Table of Contents x
1. AN 584: Timing Closure Methodology for Advanced FPGA Designs
1. AN 584: Timing Closure Methodology for Advanced FPGA Designs x
1.1. Plan Early for Timing Closure 1.2. Customize Settings Per Application 1.3. Change Fitter Placement Seeds 1.4. Planning for Timing Closure 1.5. Best Practices for Timing Closure 1.6. Resolving Common Timing Issues 1.7. Conclusion 1.8. Document Revision History for AN 584: Timing Closure Methodology for Advanced FPGA Designs
1.4. Planning for Timing Closure x
1.4.1. Timing Closure Planning at Specification Stage 1.4.2. Timing Closure Planning at Coding and Compilation Stage
1.4.1. Timing Closure Planning at Specification Stage x
1.4.1.1. Plan for the Target FPGA Device 1.4.1.2. Plan for On-Chip Debugging
1.4.2. Timing Closure Planning at Coding and Compilation Stage x
1.4.2.1. Plan for Design Hierarchy and Block Partitioning 1.4.2.2. Plan for Early Compilation of Design Blocks 1.4.2.3. Plan for Verification
1.5. Best Practices for Timing Closure x
1.5.1. Performance Planning General Guidelines 1.5.2. Follow Synchronous Design Practices 1.5.3. Follow Recommended Coding Styles 1.5.4. Constraining and Compiling Your Design
1.5.4. Constraining and Compiling Your Design x
1.5.4.1. Setting Location Constraints 1.5.4.2. Setting Proper Timing Constraints 1.5.4.3. Using Optimal Compiler Settings for Your Design
1.6. Resolving Common Timing Issues x
1.6.1. Excessive Logic Levels 1.6.2. Improper Timing Constraints 1.6.3. Handling High Fan-Out Registers 1.6.4. Metastability Issues 1.6.5. Reset Signal Related Issues 1.6.6. Small Margin Timing Constraint Failures 1.6.7. Long Compilation Times
1.6.2. Improper Timing Constraints x
1.6.2.1. Check Constraint Diagnostics
1.6.4. Metastability Issues x
1.6.4.1. Check CDC Design Assistant Rule Violations 1.6.4.2. Check CDC Report
1.6.5. Reset Signal Related Issues x
1.6.5.1. Recovery and Removal Issues
1. AN 584: Timing Closure Methodology for Advanced FPGA Designs

1.5.4.2. Setting Proper Timing Constraints

The Intel® Quartus® Prime software preserves timing constraints in Synopsys Design Constraints (.sdc) file format that uses the Tcl syntax. You can embed these .sdc constraints in a scripted compilation flow, and even create sets of .sdc files for timing optimization.

The Fitter uses the .sdc timing constraints to further optimize your design. The Timing Analyzer uses the .sdc timing constraints for static timing analysis.

By default, the Timing Analyzer assumes that all clocks in a design are related to each other, and analyzes all paths. It is possible that paths between some clock domains are false, and require no analysis. If the clocks in your design asynchronous to each other, use the set_clock_groups command in your constraint file to specify this relationship in your clock groups.

Investigate the relationship between various clocks in your design and categorize them appropriately. Supplying the appropriate constraints helps you separate real violations from false violations. Make changes in your HDL or assignments to solve issues when you identify real violations.

When you have multiple interacting clock domains, or when your design has high performance circuits, such as external memory interfaces, or clock multiplexing, ensure that the correct inter-clock constraints are present. Otherwise, the Compiler cannot focus effort on only the most critical paths.

For examples that show different scenarios for constraining your design, refer to the Intel® Quartus® Prime Timing Analyzer Cookbook and Applying Timing Constraints section of Intel® Quartus® Prime Pro Edition User Guide: Timing Analyzer.

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