AN 584: Timing Closure Methodology for Advanced FPGA Designs

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ID 683145
Date 10/08/2021
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Document Table of Contents
Document Table of Contents x
1. AN 584: Timing Closure Methodology for Advanced FPGA Designs
1. AN 584: Timing Closure Methodology for Advanced FPGA Designs x
1.1. Plan Early for Timing Closure 1.2. Customize Settings Per Application 1.3. Change Fitter Placement Seeds 1.4. Planning for Timing Closure 1.5. Best Practices for Timing Closure 1.6. Resolving Common Timing Issues 1.7. Conclusion 1.8. Document Revision History for AN 584: Timing Closure Methodology for Advanced FPGA Designs
1.4. Planning for Timing Closure x
1.4.1. Timing Closure Planning at Specification Stage 1.4.2. Timing Closure Planning at Coding and Compilation Stage
1.4.1. Timing Closure Planning at Specification Stage x
1.4.1.1. Plan for the Target FPGA Device 1.4.1.2. Plan for On-Chip Debugging
1.4.2. Timing Closure Planning at Coding and Compilation Stage x
1.4.2.1. Plan for Design Hierarchy and Block Partitioning 1.4.2.2. Plan for Early Compilation of Design Blocks 1.4.2.3. Plan for Verification
1.5. Best Practices for Timing Closure x
1.5.1. Performance Planning General Guidelines 1.5.2. Follow Synchronous Design Practices 1.5.3. Follow Recommended Coding Styles 1.5.4. Constraining and Compiling Your Design
1.5.4. Constraining and Compiling Your Design x
1.5.4.1. Setting Location Constraints 1.5.4.2. Setting Proper Timing Constraints 1.5.4.3. Using Optimal Compiler Settings for Your Design
1.6. Resolving Common Timing Issues x
1.6.1. Excessive Logic Levels 1.6.2. Improper Timing Constraints 1.6.3. Handling High Fan-Out Registers 1.6.4. Metastability Issues 1.6.5. Reset Signal Related Issues 1.6.6. Small Margin Timing Constraint Failures 1.6.7. Long Compilation Times
1.6.2. Improper Timing Constraints x
1.6.2.1. Check Constraint Diagnostics
1.6.4. Metastability Issues x
1.6.4.1. Check CDC Design Assistant Rule Violations 1.6.4.2. Check CDC Report
1.6.5. Reset Signal Related Issues x
1.6.5.1. Recovery and Removal Issues
1. AN 584: Timing Closure Methodology for Advanced FPGA Designs

1.5.4.1. Setting Location Constraints

You can specify location constraints that place logic and I/O blocks at specific locations in the chip during place and route. However, the Compiler's default logic placement is generally more suitable than specifying specific location constraints.

For example, it may not be helpful to assign a block containing a critical path to a Logic Lock region that you subsequently constrain and squeeze the path. The Fitter identifies and attempts to optimize the critical path by considering many physical constraints to find the best placement. Restricting this auto-placement can reduce performance and requires careful use. There are times when location constraints effectively aid in timing closure, directly or indirectly.

You can define Logic Lock regions or location constraints to constrain logic blocks to specific areas in the FPGA. This technique allows you to create a floorplan for your design that supports the incremental block-based compilation flow and team-based designs.

In a team-based designs, a different designer can design each major block in the project. For such cases, you define locations for each block to have its assigned area in the device. You can reserve areas in the device based on interfaces and resources, such as transceivers or RAM blocks. You can also reserve the region on a previous Fitter-assigned area.

Note: Excessive location constraints can negatively affect design performance.

Refer to Setting-Up Team-Based Designs in Intel® Quartus® Prime Pro Edition User Guide: Block-Based Design.

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