AN 584: Timing Closure Methodology for Advanced FPGA Designs

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ID 683145
Date 10/08/2021
Public
Document Table of Contents
Document Table of Contents x
1. AN 584: Timing Closure Methodology for Advanced FPGA Designs
1. AN 584: Timing Closure Methodology for Advanced FPGA Designs x
1.1. Plan Early for Timing Closure 1.2. Customize Settings Per Application 1.3. Change Fitter Placement Seeds 1.4. Planning for Timing Closure 1.5. Best Practices for Timing Closure 1.6. Resolving Common Timing Issues 1.7. Conclusion 1.8. Document Revision History for AN 584: Timing Closure Methodology for Advanced FPGA Designs
1.4. Planning for Timing Closure x
1.4.1. Timing Closure Planning at Specification Stage 1.4.2. Timing Closure Planning at Coding and Compilation Stage
1.4.1. Timing Closure Planning at Specification Stage x
1.4.1.1. Plan for the Target FPGA Device 1.4.1.2. Plan for On-Chip Debugging
1.4.2. Timing Closure Planning at Coding and Compilation Stage x
1.4.2.1. Plan for Design Hierarchy and Block Partitioning 1.4.2.2. Plan for Early Compilation of Design Blocks 1.4.2.3. Plan for Verification
1.5. Best Practices for Timing Closure x
1.5.1. Performance Planning General Guidelines 1.5.2. Follow Synchronous Design Practices 1.5.3. Follow Recommended Coding Styles 1.5.4. Constraining and Compiling Your Design
1.5.4. Constraining and Compiling Your Design x
1.5.4.1. Setting Location Constraints 1.5.4.2. Setting Proper Timing Constraints 1.5.4.3. Using Optimal Compiler Settings for Your Design
1.6. Resolving Common Timing Issues x
1.6.1. Excessive Logic Levels 1.6.2. Improper Timing Constraints 1.6.3. Handling High Fan-Out Registers 1.6.4. Metastability Issues 1.6.5. Reset Signal Related Issues 1.6.6. Small Margin Timing Constraint Failures 1.6.7. Long Compilation Times
1.6.2. Improper Timing Constraints x
1.6.2.1. Check Constraint Diagnostics
1.6.4. Metastability Issues x
1.6.4.1. Check CDC Design Assistant Rule Violations 1.6.4.2. Check CDC Report
1.6.5. Reset Signal Related Issues x
1.6.5.1. Recovery and Removal Issues
1. AN 584: Timing Closure Methodology for Advanced FPGA Designs

1.6.5. Reset Signal Related Issues

Your design can have synchronous or asynchronous reset signals. Typically resets coming into FPGA devices are asynchronous. You can convert an external asynchronous reset to a synchronous reset by feeding it through a synchronizer circuit. You can then use this signal to reset the rest of the design. This clock creates a clean reset signal that is at least one cycle wide, and synchronous to the domain in which it applies.

If you use a synchronous reset, it becomes part of the data path and affects the arrival times in the same manner as other signals in the data path. Include the reset signal in the timing analysis along with the other signals in the data path. Using a synchronous reset requires additional routing resources, such as an additional data signal.

If you use an asynchronous reset, you can globally reset all registers. This dedicated resource helps you to avoid the routing congestion that a single reset signal causes. However, a reset that is completely asynchronous can cause metastability issues. This metastability occurs because the time when the asynchronous reset is removed is asynchronous to the clock edge. If you remove the asynchronous reset signal from its asserted state in the metastability zone, some registers could fail to reset. To avoid this problem, use synchronized asynchronous reset signals.

A reset signal can reset registers asynchronously, but the reset signal is removed synchronous to a clock, reducing the possibility of registers going metastable. You can avoid unrealistic timing requirements by adding a reset synchronizer to the external asynchronous reset for each clock domain and then using the output of the synchronizers to drive the all register resets in their respective clock domains.

The following example shows an example VDD-based (voltage drain drain) reset synchronizer reset synchronizer implementation: 

module safe_reset_sync
(external_reset, clock, internal_reset) ;

input external_reset;
input clock;
output internal_reset;
reg data1, data2, q1, q2;

always@(posedge clock or negedge external_reset) begin
   if (external_reset == 1'b0) begin
      q1 <= 0;
      q2 <= 0;
   end else begin
      q1 <= 1'b1;
      q2 <= q1 ;
   end
end

endmodule

Section Content
Recovery and Removal Issues

Level Two Title