AN 584: Timing Closure Methodology for Advanced FPGA Designs

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ID 683145
Date 10/08/2021
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Document Table of Contents
Document Table of Contents x
1. AN 584: Timing Closure Methodology for Advanced FPGA Designs
1. AN 584: Timing Closure Methodology for Advanced FPGA Designs x
1.1. Plan Early for Timing Closure 1.2. Customize Settings Per Application 1.3. Change Fitter Placement Seeds 1.4. Planning for Timing Closure 1.5. Best Practices for Timing Closure 1.6. Resolving Common Timing Issues 1.7. Conclusion 1.8. Document Revision History for AN 584: Timing Closure Methodology for Advanced FPGA Designs
1.4. Planning for Timing Closure x
1.4.1. Timing Closure Planning at Specification Stage 1.4.2. Timing Closure Planning at Coding and Compilation Stage
1.4.1. Timing Closure Planning at Specification Stage x
1.4.1.1. Plan for the Target FPGA Device 1.4.1.2. Plan for On-Chip Debugging
1.4.2. Timing Closure Planning at Coding and Compilation Stage x
1.4.2.1. Plan for Design Hierarchy and Block Partitioning 1.4.2.2. Plan for Early Compilation of Design Blocks 1.4.2.3. Plan for Verification
1.5. Best Practices for Timing Closure x
1.5.1. Performance Planning General Guidelines 1.5.2. Follow Synchronous Design Practices 1.5.3. Follow Recommended Coding Styles 1.5.4. Constraining and Compiling Your Design
1.5.4. Constraining and Compiling Your Design x
1.5.4.1. Setting Location Constraints 1.5.4.2. Setting Proper Timing Constraints 1.5.4.3. Using Optimal Compiler Settings for Your Design
1.6. Resolving Common Timing Issues x
1.6.1. Excessive Logic Levels 1.6.2. Improper Timing Constraints 1.6.3. Handling High Fan-Out Registers 1.6.4. Metastability Issues 1.6.5. Reset Signal Related Issues 1.6.6. Small Margin Timing Constraint Failures 1.6.7. Long Compilation Times
1.6.2. Improper Timing Constraints x
1.6.2.1. Check Constraint Diagnostics
1.6.4. Metastability Issues x
1.6.4.1. Check CDC Design Assistant Rule Violations 1.6.4.2. Check CDC Report
1.6.5. Reset Signal Related Issues x
1.6.5.1. Recovery and Removal Issues
1. AN 584: Timing Closure Methodology for Advanced FPGA Designs

1.4.2.1. Plan for Design Hierarchy and Block Partitioning

Flat designs are generally more difficult to optimize and debug because you cannot always isolate the timing issue. Using a hierarchical design methodology offers several advantages, such as:

  • Hierarchical designs allow easier debug and optimization of individual design blocks.
  • You can assign the design hierarchy elements into logical partitions that are functionally independent.
  • These partitions allow stand-alone block verification.
  • You can use design blocks for reuse and preserve synthesis and timing results for blocks that are fully coded and meeting timing.

Planning ahead by appropriately partitioning your design reduces the need for unplanned changes when closing timing at the end of the design cycle.

When you change RTL code or Compiler settings for one block in the design, this produces different compilation results compared to previous settings. The different compilation results can cause timing violations in blocks that do not reflect the same corresponding code or setting changes. However, with the block-based incremental compilation flow, you can preserve earlier results for a block that you do not want to change.

The incremental block-based compilation feature allows you to partition a design, compile the design partitions separately, and reuse the results for unchanged partitions. You can preserve performance of unchanged blocks and reduce the number of design iterations. The performance preservation of incremental block-based compilation allows you to focus timing closure on unpreserved partitions, or on blocks that have difficulty meeting timing requirements.

Design block reuse and incremental block-based compilation flows are available in the Intel® Quartus® Prime software. For more information on effectively using these flows, refer to Intel® Quartus® Prime Pro Edition User Guide: Block-Based Design.

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