AN 584: Timing Closure Methodology for Advanced FPGA Designs

ID 683145
Date 10/08/2021
Public
Document Table of Contents

1.5.1. Performance Planning General Guidelines

The following are general guidelines for performance planning:

  • Optimize and debug incrementally by creating appropriate hierarchical blocks and partitions in your project.
  • Register all block inputs and outputs.
  • Optimize major blocks with higher than required speed when running compilation on individual design blocks.
    Note: Retaining approximately 10%-20% timing margin at the block level can help achieve timing closure after integration of the blocks.
  • Plan for the available resource types in the target device (such as the necessary RAM blocks, DSP blocks, PLLs, and transceiver locations) while coding RTL for your design.
  • Pipeline the design for better performance.