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1.1. Plan Early for Timing Closure
1.2. Customize Settings Per Application
1.3. Change Fitter Placement Seeds
1.4. Planning for Timing Closure
1.5. Best Practices for Timing Closure
1.6. Resolving Common Timing Issues
1.7. Conclusion
1.8. Document Revision History for AN 584: Timing Closure Methodology for Advanced FPGA Designs
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1.5.1. Performance Planning General Guidelines
The following are general guidelines for performance planning:
- Optimize and debug incrementally by creating appropriate hierarchical blocks and partitions in your project.
- Register all block inputs and outputs.
- Optimize major blocks with higher than required speed when running compilation on individual design blocks.
Note: Retaining approximately 10%-20% timing margin at the block level can help achieve timing closure after integration of the blocks.
- Plan for the available resource types in the target device (such as the necessary RAM blocks, DSP blocks, PLLs, and transceiver locations) while coding RTL for your design.
- Pipeline the design for better performance.
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