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33.2.2.2. Synchronizing Clock and Data Signals
The clock for the SDRAM chip (SDRAM clock) must be driven at the same frequency as the clock for the Avalon® memory-mapped interface on the SDRAM controller (controller clock). As in all synchronous designs, ensure that address, data, and control signals at the SDRAM pins are stable when a clock edge arrives. As shown in the above SDRAM Controller with Avalon® Interface block diagram, you can use an on-chip phase-locked loop (PLL) to alleviate clock skew between the SDRAM controller core and the SDRAM chip. At lower clock speeds, the PLL might not be necessary. At higher clock rates, a PLL is necessary to ensure that the SDRAM clock toggles only when signals are stable on the pins. The PLL block is not part of the SDRAM controller core. If a PLL is necessary, instantiate it manually. You can instantiate the PLL core interface or instantiate an ALTPLL IP core outside the Platform Designer system module.
If you use a PLL, tune the PLL to introduce a clock phase shift so that SDRAM clock edges arrive after synchronous signals have stabilized. See Clock, PLL and Timing Considerations sections for details.
For more information about instantiating a PLL, refer to PLL Cores chapter. The Nios® II development tools provide example hardware designs that use the SDRAM controller core in conjunction with a PLL, which you can use as a reference for your custom designs.
The Nios® II development tools are available free for download from the Intel FPGA website.