Embedded Peripherals IP User Guide

ID 683130
Date 12/18/2024
Public
Document Table of Contents
1. Introduction 2. Avalon® -ST Multi-Channel Shared Memory FIFO Core 3. Avalon® -ST Single-Clock and Dual-Clock FIFO Cores 4. Avalon® -ST Serial Peripheral Interface Core 5. SPI Core 6. SPI Agent/JTAG to Avalon® Host Bridge Cores 7. Intel eSPI Agent Core 8. eSPI to LPC Bridge Core 9. Ethernet MDIO Core 10. Intel FPGA 16550 Compatible UART Core 11. UART Core 12. JTAG UART Core 13. Intel FPGA Avalon® Mailbox Core 14. Intel FPGA Avalon® Mutex Core 15. Intel FPGA Avalon® I2C (Host) Core 16. Intel FPGA I2C Agent to Avalon® -MM Host Bridge Core 17. Intel FPGA Avalon® Compact Flash Core 18. EPCS/EPCQA Serial Flash Controller Core 19. Intel FPGA Serial Flash Controller Core 20. Intel FPGA Serial Flash Controller II Core 21. Intel FPGA Generic QUAD SPI Controller Core 22. Intel FPGA Generic QUAD SPI Controller II Core 23. Interval Timer Core 24. Intel FPGA Avalon FIFO Memory Core 25. On-Chip Memory (RAM and ROM) Intel FPGA IP 26. On-Chip Memory II (RAM or ROM) Intel FPGA IP 27. Optrex 16207 LCD Controller Core 28. PIO Core 29. PLL Cores 30. DMA Controller Core 31. Modular Scatter-Gather DMA Core 32. Scatter-Gather DMA Controller Core 33. SDRAM Controller Core 34. Tri-State SDRAM Core 35. Video Sync Generator and Pixel Converter Cores 36. Intel FPGA Interrupt Latency Counter Core 37. Performance Counter Unit Core 38. Vectored Interrupt Controller Core 39. Avalon® -ST Data Pattern Generator and Checker Cores 40. Avalon® -ST Test Pattern Generator and Checker Cores 41. System ID Peripheral Core 42. Avalon® Packets to Transactions Converter Core 43. Avalon® -ST Multiplexer and Demultiplexer Cores 44. Avalon® -ST Bytes to Packets and Packets to Bytes Converter Cores 45. Avalon® -ST Delay Core 46. Avalon® -ST Round Robin Scheduler Core 47. Avalon® -ST Splitter Core 48. Avalon® -MM DDR Memory Half Rate Bridge Core 49. Intel FPGA GMII to RGMII Converter Core 50. HPS GMII to RGMII Adapter Intel® FPGA IP 51. Intel FPGA MII to RMII Converter Core 52. HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge Core Intel® FPGA IP 53. Intel FPGA HPS EMAC to Multi-rate PHY GMII Adapter Core 54. Intel FPGA MSI to GIC Generator Core 55. Cache Coherency Translator Intel® FPGA IP 56. Altera ACE5-Lite Cache Coherency Translator Intel® FPGA IP 57. Lightweight UART Core

26.5.2. Register Descriptions

Table 291.  ECC Error Status FIFO Level Register (ECC_STATUS_FIFO_LVL)
Bit Fields Access Modified WriteValues Default Value Description
3132 eccfifo_overflow read-write writeToClear 0x0 ECC_STATUS_FIFO overflow error status. The maximum depth of ECC_STATUS_FIFO is 512.
Note: Writing to this field to clears the content of the field to 0.
[30:9] Reserved N/A 0x0 Reserved
[8:0] eccfifo_lvl read-only 0x0 Shows the current number of words stored in ECC_STATUS_FIFO.
Note:
When ECC_STATUS_FIFO is full, it will roll over to 0. The maximum depth of ECC_STATUS_FIFO is 512.
Table 292.  RAM address of ECC error status FIFO (ECC_ERR_ADDR_FIFO)The depth of ECC_ERR_ADDR_FIFO is 512.
Bit Fields Access Default Value Description
[31:26] Reserved N/A 0x0 Reserved
[25:0] ecc_err_addr read-only 0x0 The ECC_ERR_ADDR_FIFO holds the RAM’s read address(word-addressing) that has an ECC status of correctable or uncorrectable error.
Table 293.  ECC Error Status FIFO (ECC_STATUS_FIFO)The ECC_STATUS_FIFO holds the ECC status of correctable or uncorrectable error of the output data of memory.
Bit Fields Access Default Value Description
31:17 Reserved read-only 0x0 Reserved
16 RAM0_uncorrectable_ecc_err Holds the uncorrectable ECC error status of RAM 0
15:1 Reserved Reserved
0 RAM0_correctable_ecc_err Holds the correctable ECC error status of RAM 0
Table 294.  Control Register (CONTROL)
Bit Fields Access Default Value Description
[31:3] Reserved N/A 0x0 Reserved
233 eccencbypass_ena read-write 0x0 ECC Encoder Bypass feature is disabled by default. Write 1 to enable ECC Encoder Bypass feature.
1 pop_eccfifo read-write 0x0

Enabled to pop the next data from ECC_ERR_ADDR_FIFO and ECC_STATUS_FIFO.

This field will automatically reset to 0 after one data is pop out from the FIFO.

0 csr_soft_rst read-write 0x0

Enable soft reset to reset eccfifo_overflow status, ECC_ERR_ADDR_FIFO, ECC_STATUS_FIFO and parity_RAM0 registers.

This field will automatically reset to 0 after 8 clock cycles.

Table 295.  ECC parity input to RAM 0 register (PARITY_RAM0)Only applicable if parameter Enable ECC Encoder Bypass is enabled
Bit Fields Access Default Value Description
[31:8] Reserved N/A 0x0 Reserved
[7:0] parity_RAM0 read-write 0x0 8-bit parity input to RAM 0 when ECC Encoder Bypass is enabled.
32 Sticky bits
33 Only applicable if parameter Enable ECC Encoder Bypass is enabled