Visible to Intel only — GUID: iga1405555598578
Ixiasoft
Visible to Intel only — GUID: iga1405555598578
Ixiasoft
5.3.1.2. SPI Clock (sclk) Rate
This setting determines the rate of the sclk signal that synchronizes data between host and agents. The target clock rate can be specified in units of Hz, kHz or MHz. The SPI host core uses the Avalon® memory-mapped interface system clock and a clock divisor to generate sclk.
The actual frequency of sclk may not exactly match the desired target clock rate. The achievable clock values are:
< Avalon® memory-mapped interface system clock frequency> / [2, 4, 6, 8, ...]
The actual frequency achieved will not be greater than the specified target value.