Visible to Intel only — GUID: iga1401317572127
Ixiasoft
Visible to Intel only — GUID: iga1401317572127
Ixiasoft
5.2.3. Receiver Logic
The shift register and the rxdata register provide double buffering while receiving data. The rxdata register can hold a previously received data value while subsequent new data is shifting into the shift register. The receiver logic automatically transfers the shift register content to the rxdata register when a serial shift operation completes.
In host mode, the shift register is fed directly by the miso input. In agent mode, the shift register is fed directly by the mosi input. The receiver logic expects input data to arrive LSB first or MSB first, depending on the configuration of the SPI core.