Visible to Intel only — GUID: lro1402410139533
Ixiasoft
Visible to Intel only — GUID: lro1402410139533
Ixiasoft
49.5.1.1. Data Path
For transmit path, the GMII/MII data goes through the transmit pipeline register stage before going into the SDR/DDR converter block. The pipeline logic can be optionally enabled or disabled by the user during generation time.
For receive path, the GMII/MII data right after the SDR/DDR converter block goes directly to EMAC controller through Intel FPGA HPS EMAC interface splitter core; and also goes through the receive pipeline register stage. Similarly, this pipeline logic can be optionally enabled or disabled by the user during generation time.
The SDR/DDR converter block manages single data rate to double data rate conversion and vice-versa. Intel FPGA DDIO component (ALTDDIO_IN and ALTDDIO_OUT) is used to perform this task. This block also decodes collision and carrier sense condition through In-Band status detection.