Visible to Intel only — GUID: gcw1474918350860
Ixiasoft
Visible to Intel only — GUID: gcw1474918350860
Ixiasoft
48.1. Core Overview
The Avalon® Memory-Mapped (MM) Half-Rate Bridge core is a special-purpose clock-crossing bridge intended for CPUs that require low-latency access to high-speed memory. The core works under the assumption that the memory clock is twice the frequency of the CPU clock, with zero phase shift between the two. It allows high speed memory to run at full rate while providing low-latency interface for a CPU to access it by using lightweight logic that translates one single-word request into a two-word burst to a memory running at twice the clock frequency and half the width. For systems with a 8-bit DDR interface, using the Half-Rate DDR Bridge in conjunction with a DDR SDRAM high-performance memory controller creates a datapath that matches the throughput of the DDR memory to the CPU. This half-rate bridge provides the same functionality as the clock crossing bridge, but with significantly lower latency—2 cycles instead of 12.
The core’s host interface is designed to be connected to a high-speed DDR SDRAM controller and thus only supports bursting. Because the agent interface is designed to receive single-word requests, it does not support bursting. The figure below shows a system including an 8-bit DDR memory, a high-performance memory controller, the Half-Rate DDR Bridge, and a CPU.
The Avalon® -MM DDR Memory Half-Rate Bridge core has the following features and requirements:
- Platform Designer ready with Timing Analyzer constraints
- Requires host clock and agent clock to be synchronous
- Handles different bus sizes between CPU and memory
- Requires the frequency of the host clock to be double of the agent clock
- Has configurable address and data port widths in the host interface