Visible to Intel only — GUID: iga1401397402132
Ixiasoft
Visible to Intel only — GUID: iga1401397402132
Ixiasoft
32.1. Core Overview
- Memory to memory
- Data stream to memory
- Memory to data stream
The SG-DMA controller core transfers and merges non-contiguous memory to a continuous address space, and vice versa. The core reads a series of descriptors that specify the data to be transferred.
For applications requiring more than one DMA channel, multiple instantiations of the core can provide the required throughput. Each SG-DMA controller has its own series of descriptors specifying the data transfers. A single software module controls all of the DMA channels.
For the Nios® II processor, device drivers are provided in the Hardware Abstraction Layer (HAL) system library, allowing software to access the core using the provided driver.