Embedded Peripherals IP User Guide

ID 683130
Date 2/16/2024
Public

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Document Table of Contents
1. Introduction 2. Avalon® -ST Multi-Channel Shared Memory FIFO Core 3. Avalon® -ST Single-Clock and Dual-Clock FIFO Cores 4. Avalon® -ST Serial Peripheral Interface Core 5. SPI Core 6. SPI Agent/JTAG to Avalon® Host Bridge Cores 7. Intel eSPI Agent Core 8. eSPI to LPC Bridge Core 9. Ethernet MDIO Core 10. Intel FPGA 16550 Compatible UART Core 11. UART Core 12. JTAG UART Core 13. Intel FPGA Avalon® Mailbox Core 14. Intel FPGA Avalon® Mutex Core 15. Intel FPGA Avalon® I2C (Host) Core 16. Intel FPGA I2C Agent to Avalon® -MM Host Bridge Core 17. Intel FPGA Avalon® Compact Flash Core 18. EPCS/EPCQA Serial Flash Controller Core 19. Intel FPGA Serial Flash Controller Core 20. Intel FPGA Serial Flash Controller II Core 21. Intel FPGA Generic QUAD SPI Controller Core 22. Intel FPGA Generic QUAD SPI Controller II Core 23. Interval Timer Core 24. Intel FPGA Avalon FIFO Memory Core 25. On-Chip Memory (RAM and ROM) Intel FPGA IP 26. On-Chip Memory II (RAM or ROM) Intel FPGA IP 27. Optrex 16207 LCD Controller Core 28. PIO Core 29. PLL Cores 30. DMA Controller Core 31. Modular Scatter-Gather DMA Core 32. Scatter-Gather DMA Controller Core 33. SDRAM Controller Core 34. Tri-State SDRAM Core 35. Video Sync Generator and Pixel Converter Cores 36. Intel FPGA Interrupt Latency Counter Core 37. Performance Counter Unit Core 38. Vectored Interrupt Controller Core 39. Avalon® -ST Data Pattern Generator and Checker Cores 40. Avalon® -ST Test Pattern Generator and Checker Cores 41. System ID Peripheral Core 42. Avalon® Packets to Transactions Converter Core 43. Avalon® -ST Multiplexer and Demultiplexer Cores 44. Avalon® -ST Bytes to Packets and Packets to Bytes Converter Cores 45. Avalon® -ST Delay Core 46. Avalon® -ST Round Robin Scheduler Core 47. Avalon® -ST Splitter Core 48. Avalon® -MM DDR Memory Half Rate Bridge Core 49. Intel FPGA GMII to RGMII Converter Core 50. Intel FPGA MII to RMII Converter Core 51. HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge Core Intel® FPGA IP 52. Intel FPGA HPS EMAC to Multi-rate PHY GMII Adapter Core 53. Intel FPGA MSI to GIC Generator Core 54. Cache Coherency Translator Intel® FPGA IP 55. Lightweight UART Core

26.3.2.8.4. ECC Encoder Bypass

Note: ECC Encoder Bypass feature does not support Arria 10 and Cyclone 10 GX device

As described in ECC Block Diagram for M20K Memory in Figure 85, for M20K blocks, 8 parity bits are generated through the ECC encoder based on 32-bit input data width, resulting in up to a total of 40 bits of data width. In On-Chip Memory II IP, user can inject and flip the parity bits by enabling ECC Encoder Bypass feature in GUI. This feature dynamically flips the parity value generated in the encoder of M20K blocks to observe the ECC behavior through simulation.

By default, the encoder bypass is disabled, eccencbypass_ena bit of the CONTROL register is 0. To enable the encoder bypass, you are required to set eccencbypass_ena bit to 1 through the AXI-4 lite interface. The 8 parity bits can be injected to M20K through PARITY_RAM0 register.

The built-in ECC encoder values are XOR-ed with the 8 parity bits inputs to generate a new set of encoder value. When the ECC Encoder Bypass enable is low, the encoder generates the parity bits according to the data input during a write process.

Table 281.  Example of Setting the 8-Bit Parity InputThe following table shows an example to construct an 8-bit parity input.
Parity Bit Sequence ECC Feature Is the ECC Decoder able to Recognize and Correct the Data Bit?
00000001 Single-error Correction Yes
00000011 Double-adjacent-error Correction Yes
00000111 Triple-adjacent-error Correction Yes
00000101 Triple-adjacent-error Correction Yes
00010011 Non-adjacent double/triple Correction/Detection No guarantee
Table 282.  Example of Flipping the Parity Bit with User InputsThe following table shows the expected ECC status based on parity input.
Parity [7:0] ECC Status [1:0]
Internal Parity User Parity Input New Parity Correctable error (e) Uncorrectable error (ue)
1010 0011 0000 0000 1010 0011 0 0
1010 0011 0000 0001 1010 0010 1 0
1010 0011 0000 0011 1010 0000 1 0
1010 0011 0000 0111 1010 0100 1 0
1010 0011 0000 0010 1010 0001 1 0
1010 0011 0000 0110 1010 0101 1 0
1010 0011 0000 1110 1010 1101 1 0
1010 0011 0010 1001 1000 1010 X X27
1010 0011 1111 1111 0101 1100 X27 X27
27 *For non-adjacent of two-bit or more and 4-adjacent-errors are not guaranteed to be detectable or correctable.