Visible to Intel only — GUID: yyc1474908274317
Ixiasoft
Visible to Intel only — GUID: yyc1474908274317
Ixiasoft
34.1. Core Overview
The Intel® SDRAM Tri-State Controller core with Avalon® interface provides an Avalon® Memory-Mapped ( Avalon® -MM) interface to off-chip SDRAM. The SDRAM controller allows designers to create custom systems in an Intel FPGA device that connect easily to SDRAM chips. The SDRAM controller supports standard SDRAM defined by the PC100 specification.
SDRAM is commonly used in cost-sensitive applications requiring large amounts of volatile memory. While SDRAM is relatively inexpensive, control logic is required to perform refresh operations, open-row management, and other delays and command sequences. The SDRAM controller connects to one or more SDRAM chips, and handles all SDRAM protocol requirements. The SDRAM controller core presents an Avalon® -MM agent port that appears as linear memory (flat address space) to Avalon® -MM host peripherals.
The Avalon® -MM interface is latency-aware, allowing read transfers to be pipelined. The core can optionally share its address and data buses with other off-chip Avalon® -MM tri-state devices. This feature is valuable in systems that have limited I/O pins, yet must connect to multiple memory chips in addition to SDRAM.
The Intel SDRAM Tri-State Controller has the same functionality as the SDRAM Controller Core with the addition of the Tri-State feature.