Embedded Peripherals IP User Guide

ID 683130
Date 6/21/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
1. Introduction 2. Avalon® -ST Multi-Channel Shared Memory FIFO Core 3. Avalon® -ST Single-Clock and Dual-Clock FIFO Cores 4. Avalon® -ST Serial Peripheral Interface Core 5. SPI Core 6. SPI Agent/JTAG to Avalon® Host Bridge Cores 7. Intel eSPI Agent Core 8. eSPI to LPC Bridge Core 9. Ethernet MDIO Core 10. Intel FPGA 16550 Compatible UART Core 11. UART Core 12. JTAG UART Core 13. Intel FPGA Avalon® Mailbox Core 14. Intel FPGA Avalon® Mutex Core 15. Intel FPGA Avalon® I2C (Host) Core 16. Intel FPGA I2C Agent to Avalon® -MM Host Bridge Core 17. Intel FPGA Avalon® Compact Flash Core 18. EPCS/EPCQA Serial Flash Controller Core 19. Intel FPGA Serial Flash Controller Core 20. Intel FPGA Serial Flash Controller II Core 21. Intel FPGA Generic QUAD SPI Controller Core 22. Intel FPGA Generic QUAD SPI Controller II Core 23. Interval Timer Core 24. Intel FPGA Avalon FIFO Memory Core 25. On-Chip Memory (RAM and ROM) Intel FPGA IP 26. On-Chip Memory II (RAM or ROM) Intel FPGA IP 27. Optrex 16207 LCD Controller Core 28. PIO Core 29. PLL Cores 30. DMA Controller Core 31. Modular Scatter-Gather DMA Core 32. Scatter-Gather DMA Controller Core 33. SDRAM Controller Core 34. Tri-State SDRAM Core 35. Video Sync Generator and Pixel Converter Cores 36. Intel FPGA Interrupt Latency Counter Core 37. Performance Counter Unit Core 38. Vectored Interrupt Controller Core 39. Avalon® -ST Data Pattern Generator and Checker Cores 40. Avalon® -ST Test Pattern Generator and Checker Cores 41. System ID Peripheral Core 42. Avalon® Packets to Transactions Converter Core 43. Avalon® -ST Multiplexer and Demultiplexer Cores 44. Avalon® -ST Bytes to Packets and Packets to Bytes Converter Cores 45. Avalon® -ST Delay Core 46. Avalon® -ST Round Robin Scheduler Core 47. Avalon® -ST Splitter Core 48. Avalon® -MM DDR Memory Half Rate Bridge Core 49. Intel FPGA GMII to RGMII Converter Core 50. Intel FPGA MII to RMII Converter Core 51. Intel FPGA HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge Core 52. Intel FPGA HPS EMAC to Multi-rate PHY GMII Adapter Core 53. Intel FPGA MSI to GIC Generator Core 54. Cache Coherency Translator Intel® FPGA IP

31.3.1.4. Parameters

Table 296.  Component Parameters
Parameter Name Description Allowable Range
DMA Mode Transfer mode of mSGDMA. This parameter determines sub-cores instantiation to construct the mSGDMA structure. Memory-Mapped to Memory-Mapped, Memory-Mapped to Streaming, Streaming to Memory-Mapped
Data Width Data path width. This parameter affects both read host and write host data widths. 8, 16, 32, 64, 128, 256, 512, 1024
Use pre-determined host address width Use pre-determined host address width instead of automatically-determined host address width. Enable, Disable
Pre-determined host address width Minimum host address width that is required to address memory agent. 32
Expose mSGDMA read and write host's streaming ports When enabled, mSGDMA read host's data source port and mSGDMA write host's data sink port will be exposed for connection outside mSGDMA core. Enable, Disable
Data Path FIFO Depth Depth of internal data path FIFO. 16, 32, 64, 128, 256, 512, 1024, 2048, 4096
Descriptor FIFO Depth FIFO size to store descriptor count. 8, 16, 32, 64, 128, 256, 512, 1024
Response Port Option to enable response port and its port interface type Memory-Mapped, Streaming, Disabled
Maximum Transfer Length Maximum transfer length. With shorter length width being configured, the faster frequency of mSGDMA can operate in FPGA. 1KB, 2KB, 4KB, 8KB, 16KB, 32KB, 64KB, 128KB,256KB, 512KB, 1MB, 2MB, 4MB, 8MB, 16MB, 32MB, 64MB, 128MB, 256MB, 512MB, 1GB, 2GB
Transfer Type Supported transaction type Full Word Accesses Only, Aligned Accesses, Unaligned Accesses
Burst Enable Enable burst transfer Enable, Disable
No Byteenables During Writes When enabled, it forces all byte enables to high.

This option is only applicable when transfer type is set to Aligned Accesses and DMA mode is set to either Memory-mapped to Memory-Mapped or Streaming to Memory-Mapped.

When enabled, software need to handle scenario where transfer length is not multiple of data width at the end of transfer.

Note: This parameter is only available in Intel® Quartus® Prime Pro Edition software.
Enable, Disable
Maximum Burst Count Maximum burst count 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024
Force Burst Alignment Enable Disable force burst alignment. Force burst alignment forces the hosts to post bursts of length 1 until the address is aligned to a burst boundary. Enable, Disable
Enable Write Response When enabled, it turns on the write response features of the write host. After completion of the DMA transfer, the host is only notified when all the outstanding writes have been responded.
Note: This parameter is only available in Intel® Quartus® Prime Pro Edition software.
Enable, Disable
Enable Extended Feature Support Enable extended features. In order to use stride addressing, programmable burst lengths, 64-bit addressing, or descriptor tagging the enhanced features support must be enabled. Enable, Disable
Stride Addressing Enable Enable stride addressing. Stride addressing allows the DMA to read or write data that is interleaved in memory. Stride addressing cannot be enabled if the burst transfer option is enabled. Enable, Disable
Maximum Stride Words Maximum stride amount (in words) 1 – 2G
Programmable Burst Enable Enable dynamic burst programming Enable, Disable
Packet Support Enable Enable packetized transfer
Note: When PACKET_ENABLE parameter is disabled and TRANSFER_TYPE is not "Full Word Accesses Only", any unaligned transfer length will cause additional bytes to be written during the last transfer beat of the Avalon® streaming data source port of the read host core. Only with this parameter set TRUE, actual bytes transferred is meaningful for the transaction. PACKET_ENABLE only apply for ST-to-MM and MM-to-ST DMA operation mode.
Enable, Disable
Error Enable Enable error field of ST interface Enable, Disable
Error Width Error field width 1, 2, 3, 4, 5, 6, 7, 8
Channel Enable Enable channel field of ST interface Enable, Disable
Channel Width Channel field width 1, 2, 3, 4, 5, 6, 7, 8
Enable Pre-Fetching module Enables prefetcher modules, a hardware core which fetches descriptors from memory. Enable, Disable
Enable bursting on descriptor read host Enable read burst will turn on the bursting capabilities of the prefetcher's read descriptor interface. Enable, Disable
Data Width of Descriptor read/write host data path Width of the Avalon® -MM descriptor read/write data path. 32, 64, 128, 256
Maximum Burst Count on descriptor read host Maximum burst count. Enable, Disable