Embedded Peripherals IP User Guide

ID 683130
Date 6/21/2022
Public

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Document Table of Contents
1. Introduction 2. Avalon® -ST Multi-Channel Shared Memory FIFO Core 3. Avalon® -ST Single-Clock and Dual-Clock FIFO Cores 4. Avalon® -ST Serial Peripheral Interface Core 5. SPI Core 6. SPI Agent/JTAG to Avalon® Host Bridge Cores 7. Intel eSPI Agent Core 8. eSPI to LPC Bridge Core 9. Ethernet MDIO Core 10. Intel FPGA 16550 Compatible UART Core 11. UART Core 12. JTAG UART Core 13. Intel FPGA Avalon® Mailbox Core 14. Intel FPGA Avalon® Mutex Core 15. Intel FPGA Avalon® I2C (Host) Core 16. Intel FPGA I2C Agent to Avalon® -MM Host Bridge Core 17. Intel FPGA Avalon® Compact Flash Core 18. EPCS/EPCQA Serial Flash Controller Core 19. Intel FPGA Serial Flash Controller Core 20. Intel FPGA Serial Flash Controller II Core 21. Intel FPGA Generic QUAD SPI Controller Core 22. Intel FPGA Generic QUAD SPI Controller II Core 23. Interval Timer Core 24. Intel FPGA Avalon FIFO Memory Core 25. On-Chip Memory (RAM and ROM) Intel FPGA IP 26. On-Chip Memory II (RAM or ROM) Intel FPGA IP 27. Optrex 16207 LCD Controller Core 28. PIO Core 29. PLL Cores 30. DMA Controller Core 31. Modular Scatter-Gather DMA Core 32. Scatter-Gather DMA Controller Core 33. SDRAM Controller Core 34. Tri-State SDRAM Core 35. Video Sync Generator and Pixel Converter Cores 36. Intel FPGA Interrupt Latency Counter Core 37. Performance Counter Unit Core 38. Vectored Interrupt Controller Core 39. Avalon® -ST Data Pattern Generator and Checker Cores 40. Avalon® -ST Test Pattern Generator and Checker Cores 41. System ID Peripheral Core 42. Avalon® Packets to Transactions Converter Core 43. Avalon® -ST Multiplexer and Demultiplexer Cores 44. Avalon® -ST Bytes to Packets and Packets to Bytes Converter Cores 45. Avalon® -ST Delay Core 46. Avalon® -ST Round Robin Scheduler Core 47. Avalon® -ST Splitter Core 48. Avalon® -MM DDR Memory Half Rate Bridge Core 49. Intel FPGA GMII to RGMII Converter Core 50. Intel FPGA MII to RMII Converter Core 51. Intel FPGA HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge Core 52. Intel FPGA HPS EMAC to Multi-rate PHY GMII Adapter Core 53. Intel FPGA MSI to GIC Generator Core 54. Cache Coherency Translator Intel® FPGA IP

38.6.2.1. alt_ic_isr_register() versus alt_irq_register()

The enhanced API function alt_ic_isr_register() is very similar to the legacy function alt_irq_register(), with a few important differences. The differences between these two functions are best understood by examining the code in Registering an ISR with Both APIs. This example registers a timer interrupt in either the legacy API or the enhanced API, whichever is implemented in the board support package (BSP). The example is taken directly from the example code accompanying this document.

Registering an ISR with Both APIs

#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT
void timer_interrupt_latency_init (void* base, alt_u32 irq_controller_id, alt_u32 irq)
{
  /* Register the interrupt */
  alt_ic_isr_register(irq_controller_id, irq, timer_interrupt_latency_irq, base, NULL);
  /* Start timer */
  IOWR_ALTERA_AVALON_TIMER_CONTROL(base, ALTERA_AVALON_TIMER_CONTROL_ITO_MSK
  | ALTERA_AVALON_TIMER_CONTROL_START_MSK);
}
#else
void timer_interrupt_latency_init (void* base, alt_u32 irq)
{
  /* Register the interrupt */
  alt_irq_register(irq, base, timer_interrupt_latency_irq);
  /* Start timer */
  IOWR_ALTERA_AVALON_TIMER_CONTROL(base, ALTERA_AVALON_TIMER_CONTROL_ITO_MSK
  | ALTERA_AVALON_TIMER_CONTROL_START_MSK);
}
#endif

The first line of Registering an ISR with Both APIs detects whether the BSP implements the enhanced interrupt API. If the enhanced API is implemented, the timer_interrupt_latency_init() function calls the enhanced function. If not, timer_interrupt_latency_init() reverts to the legacy interrupt API function.

For an explanation of how the Nios® II Software Build Tools select which API to implement in a BSP, refer to “Interrupt Service Routines” in the Exception Handling chapter of the Nios® II Software Developer’s Handbook.

Enhanced Function alt_ic_isr_register() shows the function prototype for alt_ic_isr_register(), which registers an ISR in the enhanced API. The interrupt controller identifier (for argument ic_id) and the interrupt port number (for argument irq) are defined in system.h.

Enhanced Function alt_ic_isr_register()

extern int alt_ic_isr_register(alt_u32 ic_id,
  alt_u32 irq,
  alt_isr_func isr,
  void *isr_context,
  void *flags);

For comparison, Legacy Function alt_irq_register() shows the function prototype for alt_irq_register(), which registers an ISR in the legacy API.

Legacy Function alt_irq_register()

extern int alt_irq_register (alt_u32 id,
  void* context,
  alt_isr_func handler);

The arguments passed into alt_ic_isr_register() are slightly different from those passed into alt_irq_register(). The table below compares the arguments to the two functions.

Table 392.  Arguments to alt_ic_isr_register() versus alt_irq_register()
alt_ic_isr_register() Argument Purpose alt_irq_register() Argument
alt_u32 ic_id Unique interrupt controller ID as defined in system.h.
alt_u32 irq Interrupt request (IRQ) number as defined in system.h. alt_u32 id
alt_isr_func isr Interrupt service routine (ISR) function pointer handler
void* isr_context Optional pointer to a component-specific data structure. context
void* flags Reserved. Other EIC implementations might use this argument. None

There are other significant differences between the legacy interrupt API and the enhanced interrupt API. Some of these differences impact the ISR body itself. Notably, the two APIs employ completely different interrupt preemption models. The example code accompanying this document illustrates many of the differences.

For further information about the other functions in the HAL interrupt APIs, refer to the Exception Handling and HAL API Reference chapters of the Nios® II Software Developer’s Handbook.