Embedded Peripherals IP User Guide

ID 683130
Date 6/21/2022
Public

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Document Table of Contents
1. Introduction 2. Avalon® -ST Multi-Channel Shared Memory FIFO Core 3. Avalon® -ST Single-Clock and Dual-Clock FIFO Cores 4. Avalon® -ST Serial Peripheral Interface Core 5. SPI Core 6. SPI Agent/JTAG to Avalon® Host Bridge Cores 7. Intel eSPI Agent Core 8. eSPI to LPC Bridge Core 9. Ethernet MDIO Core 10. Intel FPGA 16550 Compatible UART Core 11. UART Core 12. JTAG UART Core 13. Intel FPGA Avalon® Mailbox Core 14. Intel FPGA Avalon® Mutex Core 15. Intel FPGA Avalon® I2C (Host) Core 16. Intel FPGA I2C Agent to Avalon® -MM Host Bridge Core 17. Intel FPGA Avalon® Compact Flash Core 18. EPCS/EPCQA Serial Flash Controller Core 19. Intel FPGA Serial Flash Controller Core 20. Intel FPGA Serial Flash Controller II Core 21. Intel FPGA Generic QUAD SPI Controller Core 22. Intel FPGA Generic QUAD SPI Controller II Core 23. Interval Timer Core 24. Intel FPGA Avalon FIFO Memory Core 25. On-Chip Memory (RAM and ROM) Intel FPGA IP 26. On-Chip Memory II (RAM or ROM) Intel FPGA IP 27. Optrex 16207 LCD Controller Core 28. PIO Core 29. PLL Cores 30. DMA Controller Core 31. Modular Scatter-Gather DMA Core 32. Scatter-Gather DMA Controller Core 33. SDRAM Controller Core 34. Tri-State SDRAM Core 35. Video Sync Generator and Pixel Converter Cores 36. Intel FPGA Interrupt Latency Counter Core 37. Performance Counter Unit Core 38. Vectored Interrupt Controller Core 39. Avalon® -ST Data Pattern Generator and Checker Cores 40. Avalon® -ST Test Pattern Generator and Checker Cores 41. System ID Peripheral Core 42. Avalon® Packets to Transactions Converter Core 43. Avalon® -ST Multiplexer and Demultiplexer Cores 44. Avalon® -ST Bytes to Packets and Packets to Bytes Converter Cores 45. Avalon® -ST Delay Core 46. Avalon® -ST Round Robin Scheduler Core 47. Avalon® -ST Splitter Core 48. Avalon® -MM DDR Memory Half Rate Bridge Core 49. Intel FPGA GMII to RGMII Converter Core 50. Intel FPGA MII to RMII Converter Core 51. Intel FPGA HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge Core 52. Intel FPGA HPS EMAC to Multi-rate PHY GMII Adapter Core 53. Intel FPGA MSI to GIC Generator Core 54. Cache Coherency Translator Intel® FPGA IP

29.4. Instantiating the PLL Core

This section describes the options available in the MegaWizard interface for the PLL core in Platform Designer.

PLL Settings Page

The PLL Settings page contains a button that launches the ALTPLL MegaWizard Plug-In Manager. Use the MegaWizard Plug-In Manager to parameterize the ALTPLL IP core. The set of available parameters depends on the target device family.

You cannot click Finish in the PLL wizard nor configure the PLL interface until you parameterize the ALTPLL IP core.

Interface Page

The Interface page configures the access modes for the optional advanced PLL status and control signals.

For each advanced signal present on the ALTPLL IP core, you can select one of the following access modes:

  • Export—Exports the signal to the top level of the Platform Designer system module.
  • Register—Maps the signal to a bit in a status or control register.

    The advanced signals are optional. If you choose not to create any of them in the ALTPLL MegaWizard Plug-In, the PLL's default behavior is as shown in below.

    You can specify the access mode for the advanced signals shown in below. The ALTPLL core signals, not displayed in this table, are automatically exported to the top level of the Platform Designer system module.

    Table 284.  ALTPLL Advanced Signal
    ALTPLL Name Input / Output Avalon® -MM PLL Wizard Name Default Behavior Description
    areset input PLL Reset Input The PLL is reset only at device configuration. This signal resets the entire Platform Designer system module, and restores the PLL to its initial settings.
    pllena input PLL Enable Input The PLL is enabled. This signal enables the PLL.

    pllena is always exported.

    pfdena input PFD Enable Input The phase-frequency detector is enabled. This signal enables the phase-frequency detector in the PLL, allowing it to lock on to changes in the clock reference.
    locked output PLL Locked Output This signal is asserted when the PLL is locked to the input clock.

    Asserting areset resets the entire Platform Designer system module, not just the PLL.

Finish

Click Finish to insert the PLL into the Platform Designer system. The PLL clock output(s) appear in the clock settings table on the Platform Designer System Contents tab.

If the PLL has external output clocks, they appear in the clock settings table like other clocks; however, you cannot use them to drive components within the Platform Designer system.

For details about using external output clocks, refer to the ALTPLL IP Core User Guide.

The Platform Designer automatically connects the PLL's reference clock input to the first available clock in the clock settings table.

If there is more than one Platform Designer system clock available, verify that the PLL is connected to the appropriate reference clock.