40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide

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ID 683114
Date 6/15/2022
Public
Document Table of Contents
Document Table of Contents x
Product Discontinuance Notification 1. About the 40- and 100-Gbps Ethernet MAC and PHY IP Core 2. Getting Started 3. Functional Description 4. Debugging the 40GbE and 100GbE Link A. 40-100GbE IP Core Example Design B. Address Map Changes for the 40-100GbE IP Core v12.0 Release C. 10GBASE-KR Registers D. Additional Information
1. About the 40- and 100-Gbps Ethernet MAC and PHY IP Core x
1.1. 40- and 100-Gbps Ethernet MAC and PHY IP Core Supported Features 1.2. 40-100GbE IP Core Device Family and Speed Grade Support 1.3. IP Core Verification 1.4. Performance and Resource Utilization 1.5. Release Information
1.2. 40-100GbE IP Core Device Family and Speed Grade Support x
1.2.1. Device Family Support 1.2.2. 40-100GbE IP Core Device Speed Grade Support
1.3. IP Core Verification x
1.3.1. Simulation Environment 1.3.2. Hardware Testing
1.4. Performance and Resource Utilization x
1.4.1. Resource Utilization for 40GbE IP Cores 1.4.2. Resource Utilization for 100GbE IP Cores
1.4.2. Resource Utilization for 100GbE IP Cores x
1.4.2.1. Resource Utilization for 100GbE CAUI–4 IP Cores
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying the 40-100GbE IP Core Parameters and Options 2.3. IP Core Parameters 2.4. Files Generated for the 40-100GbE IP Core 2.5. Simulating the IP Core 2.6. Integrating Your IP Core in Your Design 2.7. 40-100GbE IP Core Testbenches 2.8. Simulating the 40‑100GbE IP Core With the Testbenches 2.9. Compiling the Full Design and Programming the FPGA 2.10. Initializing the IP Core
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.6. Integrating Your IP Core in Your Design x
2.6.1. Pin Assignments 2.6.2. External Transceiver Reconfiguration Controller Required in Stratix V Designs 2.6.3. Placement Settings for the 40-100GbE IP Core
2.7. 40-100GbE IP Core Testbenches x
2.7.1. Testbenches with Adapters 2.7.2. Testbenches without Adapters 2.7.3. Understanding the Testbench Behavior
2.8. Simulating the 40‑100GbE IP Core With the Testbenches x
2.8.1. Generating the Testbench 2.8.2. Simulating with the Modelsim Simulator 2.8.3. Simulating with the NCSim Simulator 2.8.4. Simulating with the VCS Simulator 2.8.5. Testbench Output Example: 40GbE IP Core with Adapters 2.8.6. Testbench Output Example: 100GbE IP Core with Adapters
3. Functional Description x
3.1. High Level System Overview 3.2. 40-100GbE MAC and PHY Functional Description 3.3. Signals 3.4. Software Interface: Registers 3.5. Ethernet Glossary
3.2. 40-100GbE MAC and PHY Functional Description x
3.2.1. IP Core TX Datapath 3.2.2. IP Core TX Data Bus Interfaces 3.2.3. 40-100GbE IP Core RX Datapath 3.2.4. IP Core RX Data Bus Interfaces 3.2.5. 40GbE Lower Rate 24.24 Gbps MAC and PHY 3.2.6. 100GbE CAUI–4 PHY 3.2.7. External Reconfiguration Controller 3.2.8. Congestion and Flow Control Using Pause Frames 3.2.9. Pause Control and Generation Interface 3.2.10. Pause Control Frame and Non‑Pause Control Frame Filtering and Forwarding 3.2.11. 40-100GbE IP Core Modes of Operation 3.2.12. Link Fault Signaling Interface 3.2.13. Statistics Counters Interface 3.2.14. MAC – PHY XLGMII or CGMII Interface 3.2.15. Lane to Lane Deskew Interface 3.2.16. PCS Test Pattern Generation and Test Pattern Check 3.2.17. Transceiver PHY Serial Data Interface 3.2.18. 40GBASE-KR4 IP Core Variations 3.2.19. Control and Status Interface 3.2.20. Clocks 3.2.21. Resets
3.2.1. IP Core TX Datapath x
3.2.1.1. Preamble, Start, and SFD Insertion 3.2.1.2. Address Insertion 3.2.1.3. Length/Type Field Processing 3.2.1.4. Frame Padding 3.2.1.5. Frame Check Sequence (CRC-32) Insertion 3.2.1.6. Inter‑Packet Gap Generation and Insertion
3.2.2. IP Core TX Data Bus Interfaces x
3.2.2.1. 40-100GbE IP Core User Interface Data Bus 3.2.2.2. 40-100GbE IP Core TX Data Bus with Adapters (Avalon-ST Interface) 3.2.2.3. 40-100GbE IP Core TX Data Bus Without Adapters (Custom Streaming Interface) 3.2.2.4. Bus Quantization Effects With Adapters 3.2.2.5. User Interface to Ethernet Transmission
3.2.2.5. User Interface to Ethernet Transmission x
3.2.2.5.1. 40GbE IP Core Without Adapters 3.2.2.5.2. 100GbE IP Core Without Adapters 3.2.2.5.3. Order of Transmission
3.2.3. 40-100GbE IP Core RX Datapath x
3.2.3.1. 40-100GbE IP Core RX Filtering 3.2.3.2. 40-100GbE IP Core Preamble Processing 3.2.3.3. 40-100GbE IP Core FCS (CRC-32) Removal 3.2.3.4. 40-100GbE IP Core CRC Checking 3.2.3.5. RX CRC Forwarding 3.2.3.6. RX Automatic Pad Removal Control 3.2.3.7. Address Checking 3.2.3.8. Inter-Packet Gap 3.2.3.9. Pause Ignore
3.2.4. IP Core RX Data Bus Interfaces x
3.2.4.1. 40-100GbE IP Core User Interface Data Bus 3.2.4.2. 40-100GbE IP Core RX Data Bus with Adapters (Avalon-ST Interface) 3.2.4.3. 40-100GbE IP Core RX Data Bus Without Adapters (Custom Streaming Interface) 3.2.4.4. 100GbE IP Core RX Client Interface Examples 3.2.4.5. Error Conditions on the RX Datapath
3.2.8. Congestion and Flow Control Using Pause Frames x
3.2.8.1. Conditions Triggering XOFF Frame Transmission 3.2.8.2. Conditions Triggering XON Frame Transmission 3.2.8.3. Pause Transmission Logic
3.2.14. MAC – PHY XLGMII or CGMII Interface x
3.2.14.1. MAC to PHY Connection Interface
3.2.17. Transceiver PHY Serial Data Interface x
3.2.17.1. PCS BER Monitor
3.2.18. 40GBASE-KR4 IP Core Variations x
3.2.18.1. 40GBASE-KR4 Reconfiguration Interface 3.2.18.2. 40GBASE-KR4 Microprocessor Interface
3.3. Signals x
3.3.1. Signals of MAC and PHY Variations Without Adapters 3.3.2. Signals of MAC and PHY Variations With Adapters 3.3.3. Signals of 40-100GbE MAC‑Only IP Core Variations 3.3.4. Signals of 40-100GbE PHY‑Only IP Core Variations
3.4. Software Interface: Registers x
3.4.1. IP Core Registers 3.4.2. 40‑100GbE Example Design Registers
3.4.1. IP Core Registers x
3.4.1.1. Transceiver PHY Control and Status Registers 3.4.1.2. Lock Status Registers 3.4.1.3. Bit Error Flag Registers 3.4.1.4. PCS Hardware Error Register 3.4.1.5. BER Monitor Register 3.4.1.6. Test Mode Register 3.4.1.7. Test Pattern Counter Register 3.4.1.8. Link Fault Signaling Registers 3.4.1.9. MAC and PHY Reset Registers 3.4.1.10. PCS‑VLANE Registers 3.4.1.11. PRBS Registers 3.4.1.12. 40GBASE-KR4 Registers 3.4.1.13. MAC Configuration and Filter Registers 3.4.1.14. Pause Registers 3.4.1.15. MAC Hardware Error Register 3.4.1.16. CRC Configuration Register 3.4.1.17. MAC Feature Configuration Registers 3.4.1.18. MAC Address Registers 3.4.1.19. Statistics Registers
3.4.2. 40‑100GbE Example Design Registers x
3.4.2.1. PMD Registers 3.4.2.2. MDIO Registers 3.4.2.3. 2‑Wire Serial Interface Registers
C. 10GBASE-KR Registers x
C.1. 10GBASE-KR PHY Register Definitions
D. Additional Information x
D.1. 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide Revision History D.2. How to Contact Altera D.3. Typographic Conventions
Product Discontinuance Notification
1. About the 40- and 100-Gbps Ethernet MAC and PHY IP Core
2. Getting Started
3. Functional Description
4. Debugging the 40GbE and 100GbE Link
A. 40-100GbE IP Core Example Design
B. Address Map Changes for the 40-100GbE IP Core v12.0 Release
C. 10GBASE-KR Registers
D. Additional Information

3.4.1.1. Transceiver PHY Control and Status Registers

The TX serial rate (PCS clock) is based on the input transceiver reference clock and should be precise and stable. The RX serial rate is recovered from the remote system. The RX serial clock typically shows some instability during lock acquisition.

In variations that target a Stratix IV device, the registers in the transceiver PHY provide dynamic access to the analog configuration capability on a per channel (pin) basis. You can also use these registers to place the transceivers in loopback mode for diagnostic or error injection testing. In loopback mode, the TX output connects to the corresponding RX channel.

Table 43.  Scratch and Clock Registers for Applicable Devices

Address

Name

Applicable Device(s)

Bit

Description

HW Reset Value

Access

0x000

PHY_VERSION

Arria V GZ, Stratix IV, and Stratix V

[31:0]

40GbE/100GbE PHY IP core revision.

0x00E01310 (40GbE)

0x 00DE1310 (100GbE)

R

0x001

SCRATCH_PHY

Arria V GZ, Stratix IV, and Stratix V

[31:0]

Scratch register available for testing.

0x00000000

RW

0x002 12

CLK_TXS

Arria V GZ, Stratix IV, and Stratix V

[19:0]

TX serial clock rate monitor in KHz.

0x00000

R

0x003 12

CLK_RXS

Arria V GZ, Stratix IV, and Stratix V

[19:0]

RX serial clock rate monitor in KHz.

0x00000

R

0x004

CLK_TXC

Arria V GZ, Stratix IV, and Stratix V

[19:0]

TX core clock rate monitor in KHz.

0x00000

R

0x005

CLK_RXC

Arria V GZ, Stratix IV, and Stratix V

[19:0]

RX core clock rate monitor in KHz.

0x00000

R

0x006

—

Arria V GZ, Stratix IV, and Stratix V

–

Reserved.

—

—

0x007

—

Arria V GZ and Stratix V

–

Reserved.

—

—

0x007

GX_CTRL1

Stratix IV

[31]

When set, places the transceiver in Internal serial loopback, from TX to RX.

1’b0

RW

[30]

When asserted, the transceiver channel’s analog settings are read on the rising edge of clk_status.

1’b0

RW

[29]

When asserted, the transceiver channel’s analog settings are written on rising edge of clk_status.

1’b0

RW

[28:4]

Specifies the analog settings to write. Refer to the following table for the register fields which are read on GX_ REPLY[ 24:0]. Bits[28:4] of this register correspond to bits[24:0] of the GX_REPLY register.

0x000000

RW

[3:0]

Specifies the logical channel to select [0–9].

0x0

RW

0x008

GX_CTRL2

Arria V GZ, Stratix IV, and Stratix V

[1]

Specifies bit error inject position 1 on rising edge.

1’b0

RW

[0]

Specifies bit error inject position 0 on rising edge.

1’b0

RW

0x009

—

Arria V GZ and Stratix V

–

Reserved.

—

—

0x009

GX_REPLY

Stratix IV

[26]

Reserved.

0

R

[25]

When asserted, indicates that read data is valid.

1’b0

R

[24:0]

Contains the analog settings reported in the previous read of GX_CTRL1[28:4].

0x020080

R

Table 44.  Stratix IV Transceiver Analog Settings Register GX_CTRL1—Offset 0x007—Bits [28:4]Describes the fields in bits [28:4] of the analog settings register, GX_CTRL1. The default settings are a good starting point if you are connecting to a PMD module running at 10.3125 Gbps.

Bits

Description

HW Reset Value

Access

[28:25]

RX equalization control. The equalizer uses a pass band filter. Specifying a low value passes low frequencies. Specifying a high value passes high frequencies.

4’b0011

RW

[24:22]

RX DC gain. Sets the equalization DC gain using one of the following settings:

  • 0: 0 dB
  • 1: 3 dB
  • 2: 6 dB
  • 3: 9 dB
  • 4: 12 dB
  • 5: 15 dB
  • 6: 18 dB
  • 7: 21 dB

3’b000

RW

[21:17]

Sets the pre-emphasis for TX tap 0.

5’b10000

RW

[16:12]

Sets the pre-emphasis for TX pre-emphasis tap 1.

5’b00000

RW

[11:7]

Sets the pre-emphasis for TX pre-emphasis tap 2.

5’b10000

RW

[6:4]

TX VOD (amplitude).

3’b010

RW

If you encounter signal integrity problems using the default settings in the table, the following procedure might be helpful:

  1. Adjust VOD. A value that is too high tends to cause interference with other lanes. You should select the lowest value that functions correctly.
  2. Raise pre-emphasis tap 1 slightly. Raising tap 1 tends to help in the case of long trace length or multiple connectors causing signal loss.
  3. Adjust the equalization control. This control is roughly analogous to a stereo equalizer. It emphasizes and de-emphasizes portions of the signal by frequency.
  4. Repeat these steps, starting at step 1, making minor adjustments to all of the controls while monitoring the error rate. Note that the controls do interact.
Related Information
12 When the line rate is 10.3125 Gbps, the frequency of the serial clocks clk_tx_serial and clk_rx_serial is 10312.5/40 = 257.8125 MHz.
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