40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide

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ID 683114
Date 6/15/2022
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Document Table of Contents
Document Table of Contents x
Product Discontinuance Notification 1. About the 40- and 100-Gbps Ethernet MAC and PHY IP Core 2. Getting Started 3. Functional Description 4. Debugging the 40GbE and 100GbE Link A. 40-100GbE IP Core Example Design B. Address Map Changes for the 40-100GbE IP Core v12.0 Release C. 10GBASE-KR Registers D. Additional Information
1. About the 40- and 100-Gbps Ethernet MAC and PHY IP Core x
1.1. 40- and 100-Gbps Ethernet MAC and PHY IP Core Supported Features 1.2. 40-100GbE IP Core Device Family and Speed Grade Support 1.3. IP Core Verification 1.4. Performance and Resource Utilization 1.5. Release Information
1.2. 40-100GbE IP Core Device Family and Speed Grade Support x
1.2.1. Device Family Support 1.2.2. 40-100GbE IP Core Device Speed Grade Support
1.3. IP Core Verification x
1.3.1. Simulation Environment 1.3.2. Hardware Testing
1.4. Performance and Resource Utilization x
1.4.1. Resource Utilization for 40GbE IP Cores 1.4.2. Resource Utilization for 100GbE IP Cores
1.4.2. Resource Utilization for 100GbE IP Cores x
1.4.2.1. Resource Utilization for 100GbE CAUI–4 IP Cores
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying the 40-100GbE IP Core Parameters and Options 2.3. IP Core Parameters 2.4. Files Generated for the 40-100GbE IP Core 2.5. Simulating the IP Core 2.6. Integrating Your IP Core in Your Design 2.7. 40-100GbE IP Core Testbenches 2.8. Simulating the 40‑100GbE IP Core With the Testbenches 2.9. Compiling the Full Design and Programming the FPGA 2.10. Initializing the IP Core
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.6. Integrating Your IP Core in Your Design x
2.6.1. Pin Assignments 2.6.2. External Transceiver Reconfiguration Controller Required in Stratix V Designs 2.6.3. Placement Settings for the 40-100GbE IP Core
2.7. 40-100GbE IP Core Testbenches x
2.7.1. Testbenches with Adapters 2.7.2. Testbenches without Adapters 2.7.3. Understanding the Testbench Behavior
2.8. Simulating the 40‑100GbE IP Core With the Testbenches x
2.8.1. Generating the Testbench 2.8.2. Simulating with the Modelsim Simulator 2.8.3. Simulating with the NCSim Simulator 2.8.4. Simulating with the VCS Simulator 2.8.5. Testbench Output Example: 40GbE IP Core with Adapters 2.8.6. Testbench Output Example: 100GbE IP Core with Adapters
3. Functional Description x
3.1. High Level System Overview 3.2. 40-100GbE MAC and PHY Functional Description 3.3. Signals 3.4. Software Interface: Registers 3.5. Ethernet Glossary
3.2. 40-100GbE MAC and PHY Functional Description x
3.2.1. IP Core TX Datapath 3.2.2. IP Core TX Data Bus Interfaces 3.2.3. 40-100GbE IP Core RX Datapath 3.2.4. IP Core RX Data Bus Interfaces 3.2.5. 40GbE Lower Rate 24.24 Gbps MAC and PHY 3.2.6. 100GbE CAUI–4 PHY 3.2.7. External Reconfiguration Controller 3.2.8. Congestion and Flow Control Using Pause Frames 3.2.9. Pause Control and Generation Interface 3.2.10. Pause Control Frame and Non‑Pause Control Frame Filtering and Forwarding 3.2.11. 40-100GbE IP Core Modes of Operation 3.2.12. Link Fault Signaling Interface 3.2.13. Statistics Counters Interface 3.2.14. MAC – PHY XLGMII or CGMII Interface 3.2.15. Lane to Lane Deskew Interface 3.2.16. PCS Test Pattern Generation and Test Pattern Check 3.2.17. Transceiver PHY Serial Data Interface 3.2.18. 40GBASE-KR4 IP Core Variations 3.2.19. Control and Status Interface 3.2.20. Clocks 3.2.21. Resets
3.2.1. IP Core TX Datapath x
3.2.1.1. Preamble, Start, and SFD Insertion 3.2.1.2. Address Insertion 3.2.1.3. Length/Type Field Processing 3.2.1.4. Frame Padding 3.2.1.5. Frame Check Sequence (CRC-32) Insertion 3.2.1.6. Inter‑Packet Gap Generation and Insertion
3.2.2. IP Core TX Data Bus Interfaces x
3.2.2.1. 40-100GbE IP Core User Interface Data Bus 3.2.2.2. 40-100GbE IP Core TX Data Bus with Adapters (Avalon-ST Interface) 3.2.2.3. 40-100GbE IP Core TX Data Bus Without Adapters (Custom Streaming Interface) 3.2.2.4. Bus Quantization Effects With Adapters 3.2.2.5. User Interface to Ethernet Transmission
3.2.2.5. User Interface to Ethernet Transmission x
3.2.2.5.1. 40GbE IP Core Without Adapters 3.2.2.5.2. 100GbE IP Core Without Adapters 3.2.2.5.3. Order of Transmission
3.2.3. 40-100GbE IP Core RX Datapath x
3.2.3.1. 40-100GbE IP Core RX Filtering 3.2.3.2. 40-100GbE IP Core Preamble Processing 3.2.3.3. 40-100GbE IP Core FCS (CRC-32) Removal 3.2.3.4. 40-100GbE IP Core CRC Checking 3.2.3.5. RX CRC Forwarding 3.2.3.6. RX Automatic Pad Removal Control 3.2.3.7. Address Checking 3.2.3.8. Inter-Packet Gap 3.2.3.9. Pause Ignore
3.2.4. IP Core RX Data Bus Interfaces x
3.2.4.1. 40-100GbE IP Core User Interface Data Bus 3.2.4.2. 40-100GbE IP Core RX Data Bus with Adapters (Avalon-ST Interface) 3.2.4.3. 40-100GbE IP Core RX Data Bus Without Adapters (Custom Streaming Interface) 3.2.4.4. 100GbE IP Core RX Client Interface Examples 3.2.4.5. Error Conditions on the RX Datapath
3.2.8. Congestion and Flow Control Using Pause Frames x
3.2.8.1. Conditions Triggering XOFF Frame Transmission 3.2.8.2. Conditions Triggering XON Frame Transmission 3.2.8.3. Pause Transmission Logic
3.2.14. MAC – PHY XLGMII or CGMII Interface x
3.2.14.1. MAC to PHY Connection Interface
3.2.17. Transceiver PHY Serial Data Interface x
3.2.17.1. PCS BER Monitor
3.2.18. 40GBASE-KR4 IP Core Variations x
3.2.18.1. 40GBASE-KR4 Reconfiguration Interface 3.2.18.2. 40GBASE-KR4 Microprocessor Interface
3.3. Signals x
3.3.1. Signals of MAC and PHY Variations Without Adapters 3.3.2. Signals of MAC and PHY Variations With Adapters 3.3.3. Signals of 40-100GbE MAC‑Only IP Core Variations 3.3.4. Signals of 40-100GbE PHY‑Only IP Core Variations
3.4. Software Interface: Registers x
3.4.1. IP Core Registers 3.4.2. 40‑100GbE Example Design Registers
3.4.1. IP Core Registers x
3.4.1.1. Transceiver PHY Control and Status Registers 3.4.1.2. Lock Status Registers 3.4.1.3. Bit Error Flag Registers 3.4.1.4. PCS Hardware Error Register 3.4.1.5. BER Monitor Register 3.4.1.6. Test Mode Register 3.4.1.7. Test Pattern Counter Register 3.4.1.8. Link Fault Signaling Registers 3.4.1.9. MAC and PHY Reset Registers 3.4.1.10. PCS‑VLANE Registers 3.4.1.11. PRBS Registers 3.4.1.12. 40GBASE-KR4 Registers 3.4.1.13. MAC Configuration and Filter Registers 3.4.1.14. Pause Registers 3.4.1.15. MAC Hardware Error Register 3.4.1.16. CRC Configuration Register 3.4.1.17. MAC Feature Configuration Registers 3.4.1.18. MAC Address Registers 3.4.1.19. Statistics Registers
3.4.2. 40‑100GbE Example Design Registers x
3.4.2.1. PMD Registers 3.4.2.2. MDIO Registers 3.4.2.3. 2‑Wire Serial Interface Registers
C. 10GBASE-KR Registers x
C.1. 10GBASE-KR PHY Register Definitions
D. Additional Information x
D.1. 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide Revision History D.2. How to Contact Altera D.3. Typographic Conventions
Product Discontinuance Notification
1. About the 40- and 100-Gbps Ethernet MAC and PHY IP Core
2. Getting Started
3. Functional Description
4. Debugging the 40GbE and 100GbE Link
A. 40-100GbE IP Core Example Design
B. Address Map Changes for the 40-100GbE IP Core v12.0 Release
C. 10GBASE-KR Registers
D. Additional Information

2.3. IP Core Parameters

The 40-100GbE parameter editor provides the parameters you can set to configure the 40-100GbE IP core and simulation testbenches.

The 40-100GbE parameter editor has two tabs, the Main tab and the 40GBASE-KR4 tab. The 40GBASE-KR4 tab in the 40-100GbE parameter editor is relevant only for certain variations that target a Stratix V device; for other variations, the parameters on the tab are unavailable.

Table 11.   40-100GbE Parameters: Main TabDescribes the parameters for customizing the 40-100GbE IP core on the Main tab of the 40-100GbE parameter editor.

Parameter

Type

Range

Default Setting

Parameter Description

General Design Options

Device family

String

  • Stratix IV
  • Stratix V
  • Arria V GZ

According to the setting in the project or IP Catalog settings.

Selects the device family.

MAC configuration

String

  • 40 GbE
  • 100 GbE

100 GbE

Selects the MAC datapath width.

Core options

String

  • PHY
  • MAC
  • MAC & PHY

MAC & PHY

Selects the core components to generate.

PHY configuration 2 3 4

Integer

40 GbE:

  • 24.24 Gbps (4x6.25)
  • 40 Gbps (4x10)

100 GbE:

  • 100 Gbps (10x10)
  • CAUI-4 (4x25)

The default value depends on the MAC configuration value.

40 GbE:

  • 40 Gbps (4x10)

100 GbE:

  • 100 Gbps (10x10)

Selects the Ethernet speed and lane configuration.

MAC client interface 5

String

  • Custom–ST interface
  • Avalon–ST interface

Avalon–ST interface

Selects the Avalon–ST interface or the narrower, custom streaming client interface to the MAC.

Duplex mode 6

Integer

  • RX
  • TX
  • Full Duplex

Full Duplex

Selects datapath mode to generate.

PHY Configuration Options

PHY PLL type 2 7 8

String

  • ATX
  • CMU

ATX

Configures the PHY PLL.

PHY reference frequency 2

Integer (encoding)

The range and default settings depend on the PHY configuration.

Despite its apparent availability in the parameter editor, CAUI–4 variations do not support the 322.265625 MHz clock frequency. For correct functioning of CAUI–4 variations, you must set this parameter to the value of 644.53125 MHz.

Sets the expected incoming PHY clk_ref reference frequency. The input clock frequency must match the frequency you specify for this parameter (± 100ppm).

In Sync-E variations, the input clock frequencies for the rx_ref_clk and tx_ref_clk clocks must match the frequency you specify for this parameter, although the two clocks can be driven from different sources and need not be aligned with each other.

Advanced Design Options

Status clock rate 2

Float

  • Stratix IV: 37.5–50.0
  • Arria V GZ or Stratix V: 100.0–125.0
  • Stratix IV: 37.5
  • Arria V GZ or Stratix V: 100.0

Sets the clock rate of clk_status in MHz.

Statistics counters 5

Boolean

  • True
  • False

True

If turned on, the IP core includes built–in statistics counters. If turned off, the IP core is configured without statistics counters.

Enable SyncE support

Boolean

  • True
  • False

False

Enables or disables a separate reference clock for the RX CDR block in the transceiver and exposes the RX recovered clock as an output signal. If this option is turned on (set to true), the TX PLL and the RX CDR in the transceiver have separate input reference clocks and the RX recovered clock is visible as an IP core output signal. If it is turned off, the two PLLs share one input reference clock and the RX recovered clock is not available as an output signal.

Table 12.  40-100GbE Parameters: 40GBASE-KR4 TabDescribes the parameters for customizing a 40GBASE-KR4 40-100GbE IP core, on the 40GBASE-KR4 tab of the 40-100GbE parameter editor. The parameters on this tab are available only if the following conditions hold:
  • Your IP core targets a Stratix V device. You set the target device family for your Quartus II project or in the Quartus II software before you acess the IP Catalog.
  • You select the value of 40 GbE for the MAC configuration parameter on the Main tab.
  • You select a Core option value that includes a PHY component (PHY or MAC & PHY) on the Main tab.
  • You select the value of 40 Gbps (4x10) for the PHY configuration parameter on the Main tab.
  • You select the value of Full Duplex for the Duplex mode parameter on the Main tab.

Parameter

Type

Range

Default Setting

Parameter Description

KR4 General Options

Enable KR4

Boolean

  • True
  • False

False

If this parameter is turned on, the IP core is a 40GBASE-KR4 variation. If this parameter is turned off, the IP core is not a 40GBASE-KR4 variation, and the other parameters on this tab are not available.

Enable KR4 Reconfiguration

Boolean

  • True
  • False

True

If this parameter is turned on, the IP core supports dynamic analog reconfiguration through a dedicated reconfiguration interface. If this parameter is turned off, the IP core cannot support auto-negotiation (AN) or link training (LT) modes, and the AN and LT parameters on this tab are not available. This parameter does not affect FEC availability.

Auto-Negotiation

Enable Auto-Negotiation

Boolean

  • True
  • False

True

If this parameter is turned on, the IP core includes logic to implement auto-negotiation as defined in Clause 73 of IEEE Std 802.3ap–2007. If this parameter is turned off, the IP core does not include auto-negotiation logic and cannot perform auto-negotiation.

Currently the IP core can only negotiate to KR4 mode.

Link fail inhibit time for 40Gb Ethernet

Integer (Unit: ms)

500–510 ms

504 ms

Specifies the time before link_status is set to FAIL or OK. A link fails if the time duration specified by this parameter expires before link_status is set to OK. For more information, refer to Clause 73 Auto-Negotiation for Backplane Ethernet in IEEE Standard 802.3ap–2007.

The 40GBASE-KR4 IP core asserts the lanes_deskewed signal to indicate link_status is OK.

Auto-Negotiation Master

String

  • Lane 0
  • Lane 1
  • Lane 2
  • Lane 3

Lane 0

Selects the master channel for auto-negotiation.

Pause ability–C0

Boolean

  • True
  • False

True

If this parameter is turned on, the IP core supports symmetric pauses as defined in Annex 28B of Section 2 of IEEE Std 802.3–2008.

Pause ability–C1

Boolean

  • True
  • False

True

If this parameter is turned on, the IP core supports asymmetric pauses as defined in Annex 28B of Section 2 of IEEE Std 802.3–2008.

Link Training: PMA Parameters

VMAXRULE

Integer

0–63 60

Specifies the maximum VOD. The default value, 60, represents 1200 mV.

VMINRULE

Integer

0–63 9

Specifies the minimum VOD. The default value, 9, represents 165 mV.

VODMINRULE

Integer

0–63 24

Specifies the minimum VOD for the first tap. The default value, 24, represents 440 mV.

VPOSTRULE

Integer

0–31 31

Specifies the maximum value that the internal algorithm for pre-emphasis will ever test in determining the optimum post-tap setting.

VPRERULE

Integer

0–15 15

Specifies the maximum value that the internal algorithm for pre-emphasis will ever test in determining the optimum pre-tap setting.

PREMAINVAL

Integer

0–63 60

Specifies the Preset VOD value. This value is set by the Preset command of the link training protocol, defined in Clause 72.6.10.2.3.1 of IEEE Std 802.3ap–2007.

PREPOSTVAL

Integer

0–31 0

Specifies the preset Post-tap value.

PREPREVAL

Integer

0–15 0

Specifies the preset Pre-tap value.

INITMAINVAL

Integer

0–63 52

Specifies the initial VOD value. This value is set by the Initialize command of the link training protocol, defined in Clause 72.6.10.2.3.2 of IEEE Std 802.3ap–2007.

INITPOSTVAL

Integer

0–31 30

Specifies the initial Post-tap value.

INITPREVAL

Integer

0–15 5

Specifies the initial Pre-tap value.

Link Training: General

Enable Link Training

Boolean

  • True
  • False

True

If this parameter is turned on, the IP core includes the link training module, which configures the remote link partner TX PMD for the lowest Bit Error Rate (BER). LT is defined in Clause 72 of IEEE Std 802.3ap–2007.

Enable microcessor interface

Boolean

  • True
  • False

False

If this parameter is turned on, the IP core includes a dedicated interface through which you can control the link training.

Enable RX equalization

Boolean

  • True
  • False

False

If this parameter is turned on, the IP core includes the RX part of the link training module. This part of the link training configures local receiver RX Continuous Linear Time Equalizer (CTLE) and Decision Feedback Equalizer (DFE) to achieve the lowest Bit Error Rate (BER) .

Maximum bit error count

Integer

2n – 1 for n an integer in the range 4–12. 4095

Specifies the maximum number of errors on a lane before the Link Training Error bit (40GBASE-KR4 register offset 0xD2, bit 4, 12, 20, or 28, depending on the lane) is set, indicating an unacceptable bit error rate.

n is the width of the Bit Error Counter that is configured in the IP core. The value to which you set this parameter determines n, and thus the width of the Bit Error Counter. Because the default value of this parameter is 4095, the default width of the Bit Error Counter is 12 bits.

You can use this parameter to tune PMA settings. For example, if you see no difference in error rates between two different sets of PMA settings, you can increase the width of the bit error counter to determine if a larger counter enables you to distinguish between PMA settings.

Number of frames to send before sending actual data

Integer

  • 127
  • 255
127

Specifies the number of additional training frames the local link partner delivers to ensure that the link partner can correctly detect the local receiver state.

FEC Options

Include FEC sublayer

Boolean

  • True
  • False

False

If this parameter is turned on, the IP core includes logic to implement FEC.

Set FEC_ability bit on power up/reset

Boolean

  • True
  • False

True

If this parameter is turned on, the IP core sets the FEC ability bit (40GBASE-KR4 register offset 0xB0, bit 16) on power up and reset.

Set FEC_Enable bit on power up/reset

Boolean

  • True
  • False

True

If this parameter is turned on, the IP core sets the FEC enable bit (40GBASE-KR4 register offset 0xB0, bit 18) on power up and reset. If you turn on this parameter but do not turn on Set FEC_ability bit on power up/reset, this parameter has no effect: the IP core cannot specify the value of 1 for FEC Requested without specifying the value of 1 for FEC Ability.

Set FEC_Error_indication_ability bit on power up/reset

Boolean

  • True
  • False

True

If this parameter is turned on, the IP core is programmed by default (40GBASE-KR4 register offset 0xB0, bit 17) to report decoding errors to the PCS.

Use M20K for FEC Buffer (if available)

Boolean

  • True
  • False

True

If this parameter is turned on, the IP core is configured with a pipelined FEC buffer to support the Quartus II software in inferring M20K memory. Turning on this parameter potentially saves device resources.
Table 13.   40-100GbE PHY Parameter SettingsLists the PHY parameters that are configured automatically based on parameter values you select in the 40G/100G Ethernet parameter editor.

Parameter

40GbE Value

40GBASE-KR4 Value

100GbE Value

40GbE at 24.24 Gbps

100GbE at CAUI–4

Lanes

4

10

4

4

Data rate per lane

10312.5 Mbps

10312.5 Mbps

6250.0 Mbps

25781.25 Mbps

Available PHY reference clock frequencies

644.53125 MHz

322.265625 MHz

644.53125 MHz

322.265625 MHz

390.625 MHz

195.3125 MHz

644.53125 MHz

Related Information
2 This parameter is disabled in MAC-only operation.
3 The PHY configuration parameter is disabled when MAC configuration is set to 100GbE and Device family is not Stratix V. If the parameter is disabled, the IP core must always be set to the regular 10 Gbps PHY link option of 4 x 10.3125 or 10 x 10.3125.
4 For the Device family parameter, the CAUI-4 option requires the Stratix V GT device.
5 This parameter is disabled in PHY-only operation.
6 The Duplex mode parameter is disabled when PHY configuration is set to CAUI–4; CAUI–4 variations must always be set to the duplex configuration.
7 The PHY PLL type parameter is disabled when PHY configuration is set to CAUI–4; CAUI–4 variations must always be set to the ATX configuration.
8 The PHY PLL type parameter is disabled when the IP core targets a Stratix IV device; Stratix IV variations must always be set to the CMU configuration.
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