40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide

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ID 683114
Date 6/15/2022
Public
Document Table of Contents
Document Table of Contents x
Product Discontinuance Notification 1. About the 40- and 100-Gbps Ethernet MAC and PHY IP Core 2. Getting Started 3. Functional Description 4. Debugging the 40GbE and 100GbE Link A. 40-100GbE IP Core Example Design B. Address Map Changes for the 40-100GbE IP Core v12.0 Release C. 10GBASE-KR Registers D. Additional Information
1. About the 40- and 100-Gbps Ethernet MAC and PHY IP Core x
1.1. 40- and 100-Gbps Ethernet MAC and PHY IP Core Supported Features 1.2. 40-100GbE IP Core Device Family and Speed Grade Support 1.3. IP Core Verification 1.4. Performance and Resource Utilization 1.5. Release Information
1.2. 40-100GbE IP Core Device Family and Speed Grade Support x
1.2.1. Device Family Support 1.2.2. 40-100GbE IP Core Device Speed Grade Support
1.3. IP Core Verification x
1.3.1. Simulation Environment 1.3.2. Hardware Testing
1.4. Performance and Resource Utilization x
1.4.1. Resource Utilization for 40GbE IP Cores 1.4.2. Resource Utilization for 100GbE IP Cores
1.4.2. Resource Utilization for 100GbE IP Cores x
1.4.2.1. Resource Utilization for 100GbE CAUI–4 IP Cores
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying the 40-100GbE IP Core Parameters and Options 2.3. IP Core Parameters 2.4. Files Generated for the 40-100GbE IP Core 2.5. Simulating the IP Core 2.6. Integrating Your IP Core in Your Design 2.7. 40-100GbE IP Core Testbenches 2.8. Simulating the 40‑100GbE IP Core With the Testbenches 2.9. Compiling the Full Design and Programming the FPGA 2.10. Initializing the IP Core
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.6. Integrating Your IP Core in Your Design x
2.6.1. Pin Assignments 2.6.2. External Transceiver Reconfiguration Controller Required in Stratix V Designs 2.6.3. Placement Settings for the 40-100GbE IP Core
2.7. 40-100GbE IP Core Testbenches x
2.7.1. Testbenches with Adapters 2.7.2. Testbenches without Adapters 2.7.3. Understanding the Testbench Behavior
2.8. Simulating the 40‑100GbE IP Core With the Testbenches x
2.8.1. Generating the Testbench 2.8.2. Simulating with the Modelsim Simulator 2.8.3. Simulating with the NCSim Simulator 2.8.4. Simulating with the VCS Simulator 2.8.5. Testbench Output Example: 40GbE IP Core with Adapters 2.8.6. Testbench Output Example: 100GbE IP Core with Adapters
3. Functional Description x
3.1. High Level System Overview 3.2. 40-100GbE MAC and PHY Functional Description 3.3. Signals 3.4. Software Interface: Registers 3.5. Ethernet Glossary
3.2. 40-100GbE MAC and PHY Functional Description x
3.2.1. IP Core TX Datapath 3.2.2. IP Core TX Data Bus Interfaces 3.2.3. 40-100GbE IP Core RX Datapath 3.2.4. IP Core RX Data Bus Interfaces 3.2.5. 40GbE Lower Rate 24.24 Gbps MAC and PHY 3.2.6. 100GbE CAUI–4 PHY 3.2.7. External Reconfiguration Controller 3.2.8. Congestion and Flow Control Using Pause Frames 3.2.9. Pause Control and Generation Interface 3.2.10. Pause Control Frame and Non‑Pause Control Frame Filtering and Forwarding 3.2.11. 40-100GbE IP Core Modes of Operation 3.2.12. Link Fault Signaling Interface 3.2.13. Statistics Counters Interface 3.2.14. MAC – PHY XLGMII or CGMII Interface 3.2.15. Lane to Lane Deskew Interface 3.2.16. PCS Test Pattern Generation and Test Pattern Check 3.2.17. Transceiver PHY Serial Data Interface 3.2.18. 40GBASE-KR4 IP Core Variations 3.2.19. Control and Status Interface 3.2.20. Clocks 3.2.21. Resets
3.2.1. IP Core TX Datapath x
3.2.1.1. Preamble, Start, and SFD Insertion 3.2.1.2. Address Insertion 3.2.1.3. Length/Type Field Processing 3.2.1.4. Frame Padding 3.2.1.5. Frame Check Sequence (CRC-32) Insertion 3.2.1.6. Inter‑Packet Gap Generation and Insertion
3.2.2. IP Core TX Data Bus Interfaces x
3.2.2.1. 40-100GbE IP Core User Interface Data Bus 3.2.2.2. 40-100GbE IP Core TX Data Bus with Adapters (Avalon-ST Interface) 3.2.2.3. 40-100GbE IP Core TX Data Bus Without Adapters (Custom Streaming Interface) 3.2.2.4. Bus Quantization Effects With Adapters 3.2.2.5. User Interface to Ethernet Transmission
3.2.2.5. User Interface to Ethernet Transmission x
3.2.2.5.1. 40GbE IP Core Without Adapters 3.2.2.5.2. 100GbE IP Core Without Adapters 3.2.2.5.3. Order of Transmission
3.2.3. 40-100GbE IP Core RX Datapath x
3.2.3.1. 40-100GbE IP Core RX Filtering 3.2.3.2. 40-100GbE IP Core Preamble Processing 3.2.3.3. 40-100GbE IP Core FCS (CRC-32) Removal 3.2.3.4. 40-100GbE IP Core CRC Checking 3.2.3.5. RX CRC Forwarding 3.2.3.6. RX Automatic Pad Removal Control 3.2.3.7. Address Checking 3.2.3.8. Inter-Packet Gap 3.2.3.9. Pause Ignore
3.2.4. IP Core RX Data Bus Interfaces x
3.2.4.1. 40-100GbE IP Core User Interface Data Bus 3.2.4.2. 40-100GbE IP Core RX Data Bus with Adapters (Avalon-ST Interface) 3.2.4.3. 40-100GbE IP Core RX Data Bus Without Adapters (Custom Streaming Interface) 3.2.4.4. 100GbE IP Core RX Client Interface Examples 3.2.4.5. Error Conditions on the RX Datapath
3.2.8. Congestion and Flow Control Using Pause Frames x
3.2.8.1. Conditions Triggering XOFF Frame Transmission 3.2.8.2. Conditions Triggering XON Frame Transmission 3.2.8.3. Pause Transmission Logic
3.2.14. MAC – PHY XLGMII or CGMII Interface x
3.2.14.1. MAC to PHY Connection Interface
3.2.17. Transceiver PHY Serial Data Interface x
3.2.17.1. PCS BER Monitor
3.2.18. 40GBASE-KR4 IP Core Variations x
3.2.18.1. 40GBASE-KR4 Reconfiguration Interface 3.2.18.2. 40GBASE-KR4 Microprocessor Interface
3.3. Signals x
3.3.1. Signals of MAC and PHY Variations Without Adapters 3.3.2. Signals of MAC and PHY Variations With Adapters 3.3.3. Signals of 40-100GbE MAC‑Only IP Core Variations 3.3.4. Signals of 40-100GbE PHY‑Only IP Core Variations
3.4. Software Interface: Registers x
3.4.1. IP Core Registers 3.4.2. 40‑100GbE Example Design Registers
3.4.1. IP Core Registers x
3.4.1.1. Transceiver PHY Control and Status Registers 3.4.1.2. Lock Status Registers 3.4.1.3. Bit Error Flag Registers 3.4.1.4. PCS Hardware Error Register 3.4.1.5. BER Monitor Register 3.4.1.6. Test Mode Register 3.4.1.7. Test Pattern Counter Register 3.4.1.8. Link Fault Signaling Registers 3.4.1.9. MAC and PHY Reset Registers 3.4.1.10. PCS‑VLANE Registers 3.4.1.11. PRBS Registers 3.4.1.12. 40GBASE-KR4 Registers 3.4.1.13. MAC Configuration and Filter Registers 3.4.1.14. Pause Registers 3.4.1.15. MAC Hardware Error Register 3.4.1.16. CRC Configuration Register 3.4.1.17. MAC Feature Configuration Registers 3.4.1.18. MAC Address Registers 3.4.1.19. Statistics Registers
3.4.2. 40‑100GbE Example Design Registers x
3.4.2.1. PMD Registers 3.4.2.2. MDIO Registers 3.4.2.3. 2‑Wire Serial Interface Registers
C. 10GBASE-KR Registers x
C.1. 10GBASE-KR PHY Register Definitions
D. Additional Information x
D.1. 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide Revision History D.2. How to Contact Altera D.3. Typographic Conventions
Product Discontinuance Notification
1. About the 40- and 100-Gbps Ethernet MAC and PHY IP Core
2. Getting Started
3. Functional Description
4. Debugging the 40GbE and 100GbE Link
A. 40-100GbE IP Core Example Design
B. Address Map Changes for the 40-100GbE IP Core v12.0 Release
C. 10GBASE-KR Registers
D. Additional Information

D.1. 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide Revision History

Table 73.  Document Revision History Summarizes the new features and changes in the user guide for the 40- and 100-Gbps Ethernet MAC and PHY MegaCore function.

Date

ACDS Version

Changes

2022.06.15 14.1 Added Product Discontinuation Notice.
2014.12.15 v14.1
March 2014 v13.1 (2014.03.04)
  • Corrected device support list:
    • To include support for Stratix V GS devices.
    • To specify Final support for Stratix V devices.
  • Included "40-100GbE IP Core TX Data Bus with Adapters (Avalon-ST Interface)" section inadvertently omitted from previous version of user guide.
  • In "Frame Check Sequence (CRC-32) Insertion" section, corrected CRC_CONFIG register bit that controls TX CRC insertion.
  • Removed inconsistent statement in "40-100GbE IP core CRC Checking" section that incorrectly indicated that CRC aligns with EOP.
  • In "Statistics Counters Interface" section, fixed descriptions of the size-based frame counting signals.
  • In "Order of Transmission" section, improved figures showing byte order on the Avalon-ST interface with and without preamble pass-through enabled.
  • In "About the 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function" chapter, removed mention of 4 and 20 virtual lanes, and replaced with information correct for the Avalon-ST client-side interface. The virtual lanes are relevant only on the Ethernet link.
  • In "OpenCore Plus Time-Out Behavior" section, removed mention of nonexistent local_ready signal.
  • In "Simulating the 40-100GbE IP Core with the Testbenches" section, removed option to include or exclude waveform generation in the simulation scripts. The scripts do include this option in pre-13.1 releases.
  • Corrected topics to include links to both internal (other sections) and external (other documents and websites). Previously only one or the other appeared in each section in the document.
  • Fixed assorted typos.

November 2013

v13.1 (2013.11.04)
  • Added new 40GBASE-KR4 support with FEC option, including new parameters, signals, registers, testbench, and example design.
  • Added new parameter for Synchronous Ethernet support option to separate the reference input clocks for the RX CDR PLL and the TX PLL and make the RX recovered clock visible.
  • Added the following new signals:
    • Link fault signals visible in duplex variations: remote_fault_status and local_fault_status.
    • PHY status signals visible in MAC+PHY variations: tx_lanes_stable and lanes_deskewed.
    • New clock signals for SyncE variations: rx_clk_ref, tx_clk_ref, and rx_recovered_clk.
    • New 40GBASE-KR4 signals for analog reconfiguration.
  • Updated testbench descriptions to describe the new streamlined testbenches and the new 40GBASE-KR4 example design and testbench.
  • Updated descriptions of testbenches and example designs to clarify the user no longer needs to configure the DUT with a specific name and clock rate.
  • Updated resource utilization numbers.
  • Corrected module names in 40GbE IP core resource utilization tables.

July 2013

1.3(v13.0)

  • Corrected signal widths and descriptions in Figure 3-2 on page 3-2 and Figure 3-3 on page 3-3.
  • Corrected Avalon-ST client interface signal widths in Figure 3-5 on page 3-8, Table 3-2 on page 3-8, Figure 3-20 on page 3-23, and Table 3-6 on page 3-23.
  • Renamed and reorganized "Signals" on page 3-40.

June 2013

1.3(v13.0 software release)

  • Updated for use with version 13.0 of the Quartus II software and the MegaWizard Plug-In Manager.
  • Added preamble pass-through option. This change affects various sections in “TX Datapath” on page 3–5 and “RX Datapath” on page 3–20, and includes the addition of a new Preamble Pass-Through Configuration register (offset 0x125), described in “MAC Feature Configuration Registers” on page 3–62.
  • Added transmitter average inter-packet gap (IPG) adjustment option. This change affects “Inter‑Packet Gap Generation and Insertion” on page 3–7 and includes the addition of two new registers (IPG_DEL_PERIOD at offset 0x126 and IPG_DEL_ENABLE at offset 0x127), described in “R**MAC Feature Configuration Registers” on page 3–62.
  • Added new section “MAC Feature Configuration Registers” on page 3–62 for the new registers. Moved the description of the CRC_CONFIG register (offset 0x123) to this new section.
  • Reorganized Chapter 2, Getting Started to remove non-IP core specific information.
  • Moved instructions for IP core initialization from “Software Interface: Registers” to new section “Initializing the IP Core” on page 2–30.
  • Updated resource utilization numbers in “Performance and Resource Utilization” on page 1–5.
  • Clarified device speed grades per device family variant, in “Device Speed Grade Support” on page 1–4.
  • Clarified definitions of cut-through, store and forward, and promiscuous receive modes, in “40-100GbE IP Core Modes of Operation” on page 3–34.
  • Clarified destination address checking controls in “Address Checking ” on page 3–22 and in “MAC Address Registers” on page 3–64.
  • Removed Appendix B, Address Map Changes for 12.1, and moved information to Document Revision History entry for Quartus II software v12.1 release. The update added registers but did not change register names or offsets of existing registers.
  • Fixed descriptions of allowed transceiver reference clock frequencies and PCS clock frequencies:
    • Clarified that 644 MHz is not an allowed frequency for CAUI–4 variations, despite its presence in the parameter editor as an apparently allowed value for the PHY Reference Frequency parameter.
    • Provided correct PCS clock frequency for CAUI–4 variations.
  • Provided correct frequencies for 24.24 Gbps variations.
  • Modified “100GbE IP Core without Adapters” on page 3–14 to clarify that only two SOPs can occur on the TX custom streaming client interface during the same clock cycle.
  • Added instructions for using the example design in Appendix A, 13.0 Example Design.
  • Improved descriptions of various signals and fixed typos.

December 2012

1.2

  • Updated Slowest Supported Device Speed Grades table on page 1–4:
    • Supported speed grades for the Arria V GZ device updated to I3L, C3.
    • Supported speed grades for the Stratix V device updated to I3, C3.

November 2012

1.1

  • Updated for use with version 12.1 of the Quartus II software and the MegaWizard Plug-In Manager.
  • Updated address map.
  • Updated device family support, including the addition of the Arria V GZ device.
  • Updated interfaces for 40‑100GbE IP cores with adapters and without adapters to include the external reconfiguration controller.
  • Assignment of the FAST_SIMULATION parameter has been updated. For more information, refer to “MegaWizard Plug-In Manager Flow” on page 2–2.
  • Updated RTL hierarchy and directory structure.
  • Clocking revisions:
    • clk_din has been replaced by clk_txmac
    • clk_dout has been replaced by clk_rxmac
  • If you are transitioning from an earlier version of the IP core, you must complete the following steps:
    • Generate the 12.1 release from the MegaWizard Plug-In Manager into a new project directory; this will generate a .qip file to include in the Quartus II software project, along with the required Verilog HDL files. For more information, refer to “Getting Started” on page 2–1.
    • Quartus II software assignments from previous releases that reference the internal IP hierarchy (such as logic lock regions) must be updated for changes in the internal hierarchy. Hierarchy changes include the following:
      • The top-level Verilog in the synthesis file set has one level below it named <name of your IP instance>_inst. All further instances begin under the <name of your IP instance>_inst directory.
      • The pcs_tx, pcs_rx, and phy_csr instances now reside under phy/phy_pcs
      • The pcs_tx, pcs_rx, and phy_csr instances now reside under phy/phy_pcs
      • Nodes for the Stratix V device PMA now reside under phy/pma/pma_bridge
    • Generate example designs from the 12.1 release of the MegaWizard Plug-In Manager for a complete set of new Quartus II software assignments
    • The reconfiguration controller must be instantiated and connected to the IP core. For more information, refer to “External Reconfiguration Controller” on page 3–26 and “12.1 Example Design” on page A–1
    • Note the GXB_0PPM_CORECLK and GXB_0PPM_CORE_CLOCK Quartus II software settings are no longer required.
  • Feature additions:
    • 40GbE Lower Rate 24.24 Gbps MAC and PHY
    • 100GbE CAUI–4 PHY
    • RX Automatic Pad Removal Control
    • Pause Control Frames Filtering Control
  • Updated or added signals:
    • Top-level output and input high-speed serial lines from the transceivers
    • External reconfiguration controller
    • TX MAC to PHY connections
    • RX MAC to PHY connections
  • Added registers:
    • PAD_CONFIG at offset 0x124
    • Low Latency PHY IP Core registers for CAUI–4 at offsets 0x800–0x9FF, 0xA00–0xBFF, 0xC00–0xDFF, and 0xE00–0xFFF.

June 2012

1.0

  • Updated for use with version 12.0 of the Quartus II software.
  • Updated address map.
  • Updated device family support.
  • Updated interfaces for 40‑100GbE IP cores with adapters and without adapters. Additional interfaces include:
    • MAC and PHY asynchronous resets.
    • MAC to PHY connections.
    • Lane-to-lane deskew.
    • Statistics counters increment vectors.
    • Link fault signaling, including remote fault and local fault.
  • Updated RTL hierarchy, directory structure, and wrapper reorganization.
  • Feature additions:
    • Controllable FCS (CRC) insertion and removal.
    • Cut-through mode runt removal.
    • PCS BER monitor.
    • PCS test pattern generation and check.
    • Reduced RX destination MAC address checking from 16 addresses to 1 address.
    • Preserved FCS result.
    • Statistics counters implemented as a synthesis option.
  • Updated or added software registers:
    • Test pattern counter.
    • Link fault signaling.
    • CRC configuration.
    • MAC hardware error.
    • MAC and PHY resets.
    • PCS hardware error.
    • BER monitor.
    • Test mode.
    • MAC address.
    • Statistics counters: roll-overs and increment vectors.
  • Clocking revisions:
    • clk50 has been removed and replaced by clk_status.
    • clk_din/clk_txmac and clk_dout/clk_rxmac have been added as TX and RX input clocks.
  • Additional parameters: STATS_CNTRS_OPTION and FAST_SIMULATION.
  • Updated testbenches and simulation examples.
  • Updated reset signals and reset bits.
  • Additional information regarding oversized frames.

November 2011

Early Access

  • Corrected the following issues in the MegaCore function:
    • Corrected sequence ordered set encoding in PCS.
    • Corrected error control block encoding in PCS.
    • Corrected pause logic to accomodate multiple pause requests.
  • Timing performance improvements:
    • Optimized RTL for better timing performance.
  • Clocking revisions:
    • clk_status and clk_csr now support 100 MHz operation in Stratix V devices for PHY IP calibration.
  • Added Stratix V resource utilization information.
  • Updated definition l <n> _rx_ready to include fact that the RX MAC can only be backpressured for a limited number of cycles; consequently, the application should be able to accept a continuous data stream.

September 2011

Early Access

  • Feature additions:
    • Added optional adapters that guarantee the start of packet is always in lane 0.
    • Added full statistics counters module.
    • Modified and improved register map.
  • Provided separate product ID and ordering code for 40GbE and 100GbE MAC and PHY.
  • Corrected the following issues in the MegaCore function:
    • Data is no longer reversed in the adapters.
    • The multicast address is used for the multicast pause frames.
    • The pause state machine loads new pause times as required.
    • Short frames on the TX datapath are converted correctly from 8 words to 5 words.
  • Updated resource utilization numbers.
  • User guide enhancements:
    • Rewrote and added new sections and drawings.
    • Added default values of registers after reset.
    • Combined 40GbE and 100GbE in one user guide.
    • Corrected description of PMD_CMD_CONFIG bit. Writing a 1 enables the PMD.
    • Corrected description of PMD_CMD_CONFIG bit. Writing a 1 enables the PMD.
    • Corrected description of RX_AGGREGATE register. Definitions for bit[0] and bit[1] were reversed.
    • Corrected description of pause_quanta.
    • Corrected descriptions of Figure 3–10 on page 3–11 through Figure 3–12 on page 3–12.
  • Removed din_in_packet from Figure 3–2 on page 3–3.

July 2010

Early Access

Initial early access release.

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