40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide

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ID 683114
Date 6/15/2022
Public
Document Table of Contents
Document Table of Contents x
Product Discontinuance Notification 1. About the 40- and 100-Gbps Ethernet MAC and PHY IP Core 2. Getting Started 3. Functional Description 4. Debugging the 40GbE and 100GbE Link A. 40-100GbE IP Core Example Design B. Address Map Changes for the 40-100GbE IP Core v12.0 Release C. 10GBASE-KR Registers D. Additional Information
1. About the 40- and 100-Gbps Ethernet MAC and PHY IP Core x
1.1. 40- and 100-Gbps Ethernet MAC and PHY IP Core Supported Features 1.2. 40-100GbE IP Core Device Family and Speed Grade Support 1.3. IP Core Verification 1.4. Performance and Resource Utilization 1.5. Release Information
1.2. 40-100GbE IP Core Device Family and Speed Grade Support x
1.2.1. Device Family Support 1.2.2. 40-100GbE IP Core Device Speed Grade Support
1.3. IP Core Verification x
1.3.1. Simulation Environment 1.3.2. Hardware Testing
1.4. Performance and Resource Utilization x
1.4.1. Resource Utilization for 40GbE IP Cores 1.4.2. Resource Utilization for 100GbE IP Cores
1.4.2. Resource Utilization for 100GbE IP Cores x
1.4.2.1. Resource Utilization for 100GbE CAUI–4 IP Cores
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying the 40-100GbE IP Core Parameters and Options 2.3. IP Core Parameters 2.4. Files Generated for the 40-100GbE IP Core 2.5. Simulating the IP Core 2.6. Integrating Your IP Core in Your Design 2.7. 40-100GbE IP Core Testbenches 2.8. Simulating the 40‑100GbE IP Core With the Testbenches 2.9. Compiling the Full Design and Programming the FPGA 2.10. Initializing the IP Core
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.6. Integrating Your IP Core in Your Design x
2.6.1. Pin Assignments 2.6.2. External Transceiver Reconfiguration Controller Required in Stratix V Designs 2.6.3. Placement Settings for the 40-100GbE IP Core
2.7. 40-100GbE IP Core Testbenches x
2.7.1. Testbenches with Adapters 2.7.2. Testbenches without Adapters 2.7.3. Understanding the Testbench Behavior
2.8. Simulating the 40‑100GbE IP Core With the Testbenches x
2.8.1. Generating the Testbench 2.8.2. Simulating with the Modelsim Simulator 2.8.3. Simulating with the NCSim Simulator 2.8.4. Simulating with the VCS Simulator 2.8.5. Testbench Output Example: 40GbE IP Core with Adapters 2.8.6. Testbench Output Example: 100GbE IP Core with Adapters
3. Functional Description x
3.1. High Level System Overview 3.2. 40-100GbE MAC and PHY Functional Description 3.3. Signals 3.4. Software Interface: Registers 3.5. Ethernet Glossary
3.2. 40-100GbE MAC and PHY Functional Description x
3.2.1. IP Core TX Datapath 3.2.2. IP Core TX Data Bus Interfaces 3.2.3. 40-100GbE IP Core RX Datapath 3.2.4. IP Core RX Data Bus Interfaces 3.2.5. 40GbE Lower Rate 24.24 Gbps MAC and PHY 3.2.6. 100GbE CAUI–4 PHY 3.2.7. External Reconfiguration Controller 3.2.8. Congestion and Flow Control Using Pause Frames 3.2.9. Pause Control and Generation Interface 3.2.10. Pause Control Frame and Non‑Pause Control Frame Filtering and Forwarding 3.2.11. 40-100GbE IP Core Modes of Operation 3.2.12. Link Fault Signaling Interface 3.2.13. Statistics Counters Interface 3.2.14. MAC – PHY XLGMII or CGMII Interface 3.2.15. Lane to Lane Deskew Interface 3.2.16. PCS Test Pattern Generation and Test Pattern Check 3.2.17. Transceiver PHY Serial Data Interface 3.2.18. 40GBASE-KR4 IP Core Variations 3.2.19. Control and Status Interface 3.2.20. Clocks 3.2.21. Resets
3.2.1. IP Core TX Datapath x
3.2.1.1. Preamble, Start, and SFD Insertion 3.2.1.2. Address Insertion 3.2.1.3. Length/Type Field Processing 3.2.1.4. Frame Padding 3.2.1.5. Frame Check Sequence (CRC-32) Insertion 3.2.1.6. Inter‑Packet Gap Generation and Insertion
3.2.2. IP Core TX Data Bus Interfaces x
3.2.2.1. 40-100GbE IP Core User Interface Data Bus 3.2.2.2. 40-100GbE IP Core TX Data Bus with Adapters (Avalon-ST Interface) 3.2.2.3. 40-100GbE IP Core TX Data Bus Without Adapters (Custom Streaming Interface) 3.2.2.4. Bus Quantization Effects With Adapters 3.2.2.5. User Interface to Ethernet Transmission
3.2.2.5. User Interface to Ethernet Transmission x
3.2.2.5.1. 40GbE IP Core Without Adapters 3.2.2.5.2. 100GbE IP Core Without Adapters 3.2.2.5.3. Order of Transmission
3.2.3. 40-100GbE IP Core RX Datapath x
3.2.3.1. 40-100GbE IP Core RX Filtering 3.2.3.2. 40-100GbE IP Core Preamble Processing 3.2.3.3. 40-100GbE IP Core FCS (CRC-32) Removal 3.2.3.4. 40-100GbE IP Core CRC Checking 3.2.3.5. RX CRC Forwarding 3.2.3.6. RX Automatic Pad Removal Control 3.2.3.7. Address Checking 3.2.3.8. Inter-Packet Gap 3.2.3.9. Pause Ignore
3.2.4. IP Core RX Data Bus Interfaces x
3.2.4.1. 40-100GbE IP Core User Interface Data Bus 3.2.4.2. 40-100GbE IP Core RX Data Bus with Adapters (Avalon-ST Interface) 3.2.4.3. 40-100GbE IP Core RX Data Bus Without Adapters (Custom Streaming Interface) 3.2.4.4. 100GbE IP Core RX Client Interface Examples 3.2.4.5. Error Conditions on the RX Datapath
3.2.8. Congestion and Flow Control Using Pause Frames x
3.2.8.1. Conditions Triggering XOFF Frame Transmission 3.2.8.2. Conditions Triggering XON Frame Transmission 3.2.8.3. Pause Transmission Logic
3.2.14. MAC – PHY XLGMII or CGMII Interface x
3.2.14.1. MAC to PHY Connection Interface
3.2.17. Transceiver PHY Serial Data Interface x
3.2.17.1. PCS BER Monitor
3.2.18. 40GBASE-KR4 IP Core Variations x
3.2.18.1. 40GBASE-KR4 Reconfiguration Interface 3.2.18.2. 40GBASE-KR4 Microprocessor Interface
3.3. Signals x
3.3.1. Signals of MAC and PHY Variations Without Adapters 3.3.2. Signals of MAC and PHY Variations With Adapters 3.3.3. Signals of 40-100GbE MAC‑Only IP Core Variations 3.3.4. Signals of 40-100GbE PHY‑Only IP Core Variations
3.4. Software Interface: Registers x
3.4.1. IP Core Registers 3.4.2. 40‑100GbE Example Design Registers
3.4.1. IP Core Registers x
3.4.1.1. Transceiver PHY Control and Status Registers 3.4.1.2. Lock Status Registers 3.4.1.3. Bit Error Flag Registers 3.4.1.4. PCS Hardware Error Register 3.4.1.5. BER Monitor Register 3.4.1.6. Test Mode Register 3.4.1.7. Test Pattern Counter Register 3.4.1.8. Link Fault Signaling Registers 3.4.1.9. MAC and PHY Reset Registers 3.4.1.10. PCS‑VLANE Registers 3.4.1.11. PRBS Registers 3.4.1.12. 40GBASE-KR4 Registers 3.4.1.13. MAC Configuration and Filter Registers 3.4.1.14. Pause Registers 3.4.1.15. MAC Hardware Error Register 3.4.1.16. CRC Configuration Register 3.4.1.17. MAC Feature Configuration Registers 3.4.1.18. MAC Address Registers 3.4.1.19. Statistics Registers
3.4.2. 40‑100GbE Example Design Registers x
3.4.2.1. PMD Registers 3.4.2.2. MDIO Registers 3.4.2.3. 2‑Wire Serial Interface Registers
C. 10GBASE-KR Registers x
C.1. 10GBASE-KR PHY Register Definitions
D. Additional Information x
D.1. 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide Revision History D.2. How to Contact Altera D.3. Typographic Conventions
Product Discontinuance Notification
1. About the 40- and 100-Gbps Ethernet MAC and PHY IP Core
2. Getting Started
3. Functional Description
4. Debugging the 40GbE and 100GbE Link
A. 40-100GbE IP Core Example Design
B. Address Map Changes for the 40-100GbE IP Core v12.0 Release
C. 10GBASE-KR Registers
D. Additional Information

3.4.1.19. Statistics Registers

The statistics registers count Ethernet traffic and errors. The 64-bit statistics registers are designed to roll over, to ensure timing closure on the FPGA. However, these registers should never roll over if the link is functioning properly. The statistics registers check the size of frames, which includes the following fields:

  • Size of the destination address
  • Size of the source address
  • Size of the data
  • Four bytes of CRC

The statistics counters module is a synthesis option. The statistics registers are counters that are implemented inside the CSR. When you turn on the Statistics counters parameter in the 40-100GbE parameter editor, the counters are implemented in the CSR. When you turn off the Statistics counters parameter in the 40-100GbE parameter editor, the counters are not implemented in the CSR, and read access to the counters returns read data equal to 0.

To read the value of a statistics register without clearing it, write the value of 0x4 to the MAC_CMD_config register. To read the value of a statistics register and reset the counters, write the value of 0xC to the MAC_CMD_config register.

Table 65.  Transmit Side Statistics Registers The initial value after reset is 0 for all statistics registers.

Address

Name-

Description

Access

0x200

CNTR_TX_64B_LO

Number of 64-byte transmitted frames, including the CRC field but excluding the preamble and SFD bytes (lower 32 bits)

RO

0x201

CNTR_TX_64B_HI

Number of 64-byte transmitted frames (upper 32 bits), including the CRC field but excluding the preamble and SFD bytes (upper 32 bits)

RO

0x202

CNTR_TX_65to127B_LO

Number of transmitted frames between 65–127 bytes (lower 32 bits)

RO

0x203

CNTR_TX_65to127B_HI

Number of transmitted frames between 65–127 bytes (upper 32 bits)

RO

0x204

CNTR_TX_128to255B_LO

Number of transmitted frames between 128–255 bytes (lower 32 bits)

RO

0x205

CNTR_TX_128to255B_HI

Number of transmitted frames between 128–255 bytes (upper 32 bits)

RO

0x206

CNTR_TX_256to511B_LO

Number of transmitted frames between 256–511 bytes (lower 32 bits)

RO

0x207

CNTR_TX_256to511B_HI

Number of transmitted frames between 256–511 bytes (upper 32 bits)

RO

0x208

CNTR_TX_512to1023B_LO

Number of transmitted frames between 512–1023 bytes (lower 32 bits)

RO

0x209

CNTR_TX_512to1023B_HI

Number of transmitted frames between 512–1023 bytes (upper 32 bits)

RO

0x20A

CNTR_TX_1024to1518B_LO

Number of transmitted frames between 1024–1518 bytes (lower 32 bits)

RO

0x20B

CNTR_TX_1024to1518B_HI

Number of transmitted frames between 1024–1518 bytes (upper 32 bits)

RO

0x20C

CNTR_TX_1519toMAXB_LO

Number of transmitted frames between 1519 and max size defined in 0x103 (lower 32 bits)

RO

0x20D

CNTR_TX_1519toMAXB_HI

Number of transmitted frames between 1519 and max size defined in 0x103 (upper 32 bits)

RO

0x20E

CNTR_TX_OVERSIZE_LO

Number of oversized frames transmitted (lower 32 bits)

RO

0x20F

CNTR_TX_OVERSIZE_HI

Number of oversized frames transmitted (upper 32 bits)

RO

0x210

CNTR_TX_MCAST_DATA_ERR_LO

Number of errored multicast frames transmitted, excluding control frames (lower 32 bits)

RO

0x211

CNTR_TX_MCAST_DATA_ERR_HI

Number of errored multicast frames transmitted, excluding control frames (upper 32 bits)

RO

0x212

CNTR_TX_MCAST_DATA_OK_LO

Number of valid multicast frames transmitted, excluding control frames (lower 32 bits)

RO

0x213

CNTR_TX_MCAST_DATA_OK_HI

Number of valid multicast frames transmitted, excluding control frames (upper 32 bits)

RO

0x214

CNTR_TX_BCAST_DATA_ERR_LO

Number of errored broadcast frames transmitted, excluding control frames (lower 32 bits)

RO

0x215

CNTR_TX_BCAST_DATA_ERR_HI

Number of errored broadcast frames transmitted, excluding control frames (upper 32 bits)

RO

0x216

CNTR_TX_BCAST_DATA_OK_LO

Number of valid broadcast frames transmitted, excluding control frames (lower 32 bits)

RO

0x217

CNTR_TX_BCAST_DATA_OK_HI

Number of valid broadcast frames transmitted, excluding control frames (upper 32 bits)

RO

0x218

CNTR_TX_UCAST_DATA_ERR_LO

Number of errored unicast frames transmitted, excluding control frames (lower 32 bits)

RO

0x219

CNTR_TX_UCAST_DATA_ERR_HI

Number of errored unicast frames transmitted, excluding control frames (upper 32 bits)

RO

0x21A

CNTR_TX_UCAST_DATA_OK_LO

Number of valid unicast frames transmitted, excluding control frames (lower 32 bits)

RO

0x21B

CNTR_TX_UCAST_DATA_OK_HI

Number of valid unicast frames transmitted, excluding control frames (upper 32 bits)

RO

0x21C

CNTR_TX_MCAST_CTRL_LO

Number of valid multicast frames transmitted (lower 32 bits)

RO

0x21D

CNTR_TX_MCAST_CTRL_HI

Number of valid multicast frames transmitted (upper 32 bits)

RO

0x21E

CNTR_TX_BCAST_CTRL_LO

Number of valid broadcast frames transmitted (lower 32 bits)

RO

0x21F

CNTR_TX_BCAST_CTRL_HI

Number of valid broadcast frames transmitted (upper 32 bits)

RO

0x220

CNTR_TX_UCAST_CTRL_LO

Number of valid unicast frames transmitted (lower 32 bits)

RO

0x221

CNTR_TX_UCAST_CTRL_HI

Number of valid unicast frames transmitted (upper 32 bits)

RO

0x222

CNTR_TX_PAUSE_LO

Number of valid pause frames transmitted (lower 32 bits)

RO

0x223

CNTR_TX_PAUSE_HI

Number of valid pause frames transmitted (upper 32 bits)

RO

0x224

CNTR_TX_FRAGMENTS_LO

Number of transmitted frames of less than 64 bytes reporting a CRC error (lower 32 bits)

RO

0x225

CNTR_TX_FRAGMENTS_HI

Number of transmitted frames of less than 64 bytes reporting a CRC error (upper 32 bits)

RO

0x226

CNTR_TX_JABBERS_LO

Number of transmitted oversized frames reporting a CRC error (lower 32 bits)

RO

0x227

CNTR_TX_JABBERS_HI

Number of transmitted oversized frames reporting a CRC error (upper 32 bits)

RO

0x228

CNTR_TX_CRCERR_LO

Number of transmitted frames between 64 bytes and the value configured in 0x103 register reporting a CRC error (lower 32 bits)

RO

0x229

CNTR_TX_CRCERR_HI

Number of transmitted frames between 64 bytes and the value configured in 0x103 register reporting a CRC error (upper 32 bits)

RO

TX Packet Statistics

0x22A

CNTR_TX_ST_LO

Number of transmitted frame starts, excluding pause frames (lower 32 bits)

RO

0x22B

CNTR_TX_ST_HI

Number of transmitted frame starts, excluding pause frames (upper 32 bits)

RO

0x22C

CNTR_TX_DB_LO

Number of transmitted data blocks (number of full symbols (2 or 5 words, depending on the variation) that pass from the MAC to the PHY that contain at least some data)(lower 32 bits)

RO

0x22D

CNTR_TX_DB_HI

Number of transmitted data blocks (number of full symbols (2 or 5 words, depending on the variation) that pass from the MAC to the PHY that contain at least some data) (upper 32 bits)

RO

Table 66.  Receive Side Statistics Registers

Address

Name-

Description

Access

0x280

CNTR_RX_64B_LO

Number of 64-byte received frames (lower 32 bits), including the CRC field but excluding the preamble and SFD bytes

RO

0x281

CNTR_RX_64B_HI

Number of 64-byte received frames (upper 32 bits), including the CRC field but excluding the preamble and SFD bytes

RO

0x282

CNTR_RX_65to127B_LO

Number of received frames between 65–127 bytes (lower 32 bits)

RO

0x283

CNTR_RX_65to127B_HI

Number of received frames between 65–127 bytes (upper 32 bits)

RO

0x284

CNTR_RX_128to255B_LO

Number of received frames between 128 –255 bytes (lower 32 bits)

RO

0x285

CNTR_RX_128to255B_HI

Number of received frames between 128 –255 bytes (upper 32 bits)

RO

0x286

CNTR_RX_256to511B_LO

Number of received frames between 256 –511 bytes (lower 32 bits)

RO

0x287

CNTR_RX_256to511B_HI

Number of received frames between 256 –511 bytes (upper 32 bits)

RO

0x288

CNTR_RX_512to1023B_LO

Number of received frames between 512–1023 bytes (lower 32 bits)

RO

0x289

CNTR_RX_512to1023B_HI

Number of received frames between 512 –1023 bytes (upper 32 bits)

RO

0x28A

CNTR_RX_1024to1518B_LO

Number of received frames between 1024–1518 bytes (lower 32 bits)

RO

0x28B

CNTR_RX_1024to1518B_HI

Number of received frames between 1024–1518 bytes (upper 32 bits)

RO

0x28C

CNTR_RX_1519toMAXB_LO

Number of received frames between 1519 and the maximum size defined in 0x103 (lower 32 bits)

RO

0x18D

CNTR_RX_1519toMAXB_HI

Number of received frames between 1519 and the maximum size defined in 0x103 (upper 32 bits)

RO

0x28E

CNTR_RX_OVERSIZE_LO

Number of oversized frames received (lower 32 bits)

RO

0x28F

CNTR_RX_OVERSIZE_HI

Number of oversized frames received (upper 32 bits)

RO

0x290

CNTR_RX_MCAST_DATA_ERR_LO

Number of errored multicast frames received, excluding control frames (lower 32 bits)

RO

0x291

CNTR_RX_MCAST_DATA_ERR_HI

Number of errored multicast frames received, excluding control frames (upper 32 bits)

RO

0x292

CNTR_RX_MCAST_DATA_OK_LO

Number of valid multicast frames received, excluding control frames (lower 32 bits)

RO

0x293

CNTR_RX_MCAST_DATA_OK_HI

Number of valid multicast frames received, excluding control frames (upper 32 bits)

RO

0x294

CNTR_RX_BCAST_DATA_ERR_LO

Number of errored broadcast frames received, excluding control frames (lower 32 bits)

RO

0x295

CNTR_RX_BCAST_DATA_ERR_HI

Number of errored broadcast frames received, excluding control frames (upper 32 bits)

RO

0x296

CNTR_RX_BCAST_DATA_OK_LO

Number of valid broadcast frames received, excluding control frames (lower 32 bits)

RO

0x297

CNTR_RX_BCAST_DATA_OK_HI

Number of valid broadcast frames received, excluding control frames (upper 32 bits)

RO

0x298

CNTR_RX_UCAST_DATA_ERR_LO

Number of errored unicast frames received, excluding control frames (lower 32 bits)

RO

0x299

CNTR_RX_UCAST_DATA_ERR_HI

Number of errored unicast frames received, excluding control frames (upper 32 bits)

RO

0x29A

CNTR_RX_UCAST_DATA_OK_LO

Number of valid unicast frames received, excluding control frames (lower 32 bits)

RO

0x29B

CNTR_RX_UCAST_DATA_OK_HI

Number of valid unicast frames received, excluding control frames (upper 32 bits)

RO

0x29C

CNTR_RX_MCAST_CTRL_LO

Number of valid multicast frames received, excluding data frames (lower 32 bits)

RO

0x29D

CNTR_RX_MCAST_CTRL_HI

Number of valid multicast frames received, excluding data frames (upper 32 bits)

RO

0x29E

CNTR_RX_BCAST_CTRL_LO

Number of valid broadcast frames received, excluding data frames (lower 32 bits)

RO

0x29F

CNTR_RX_BCAST_CTRL_HI

Number of valid broadcast frames received, excluding data frames (upper 32 bits)

RO

0x2A0

CNTR_RX_UCAST_CTRL_LO

Number of valid unicast frames received, excluding data frames (lower 32 bits)

RO

0x2A1

CNTR_RX_UCAST_CTRL_HI

Number of valid unicast frames received, excluding data frames (upper 32 bits)

RO

0x2A2

CNTR_RX_PAUSE_LO

Number of valid pause frames received (lower 32 bits)

RO

0x2A3

CNTR_RX_PAUSE_HI

Number of valid pause frames received (upper 32 bits)

RO

0x2A4

CNTR_RX_FRAGMENTS_LO

Number of received frames less than 64 bytes and reporting a CRC error (lower 32 bits)

RO

0x2A5

CNTR_RX_FRAGMENTS_HI

Number of received frames less than 64 bytes and reporting a CRC error (upper 32 bits)

RO

0x2A6

CNTR_RX_JABBERS_LO

Number of received oversized frames reporting a CRC error (lower 32 bits)

RO

0x2A7

CNTR_RX_JABBERS_HI

Number of received oversized frames reporting a CRC error (upper 32 bits)

RO

0x2A8

CNTR_RX_CRCERR_LO

Number of received frames between the length of 64 and the value configured in 0x103 register with CRC error (lower 32 bits)

RO

0x2A9

CNTR_RX_CRCERR_HI

Number of received frames between the length of 64 and the value configured in 0x103 register with CRC error (upper 32 bits)

RO

RX Packet Statistics

0x2AA

CNTR_RX_ST_LO

Number of received frame starts (lower 32 bits)

RO

0x2AB

CNTR_RX_ST_HI

Number of received frame starts (upper 32 bits)

RO

0x2AC

CNTR_RX_DB_LO

Number of received data blocks (number of full symbols (2 or 5 words, depending on the variation) that pass from the PHY to the MAC that contain at least some data) (lower 32 bits)

RO

0x2AD

CNTR_RX_DB_HI

Number of received data blocks (number of full symbols (2 or 5 words, depending on the variation) that pass from the PHY to the MAC that contain at least some data) (upper 32 bits)

RO

0x2AE

CNTR_RXF_ST_LO

Number of accepted frame starts (lower 32 bits)

RO

0x2AF

CNTR_RXF_ST_HI

Number of accepted frame starts (upper 32 bits)

RO

0x2B0

CNTR_RXF_DB_LO

Number of accepted data blocks (number of full symbols (2 or 5 words, depending on the variation) that pass from the PHY to the MAC that contain at least some data and that the MAC accepts) (lower 32 bits)

RO

0x2B1

CNTR_RXF_DB_HI

Number of accepted data blocks (number of full symbols (2 or 5 words, depending on the variation) that pass from the PHY to the MAC that contain at least some data and that the MAC accepts) (upper 32 bits)

RO

0x2B2

CNTR_RXF_LONG

Number of packets aborted due to excessive length.

RO

0x2B3

Reserved

0x2B4

CNTR_RX_EBLK

Number of received blocks with XGMII and CGMII errors. The number of received error blocks is equal to the RX symbol error counter defined by Operation Administration and Maintenance (OAM) in accordance with IEEE standard 802.3ba.

RO

0x2B5

Reserved

0x2B6

CNTR_RX_RUNT

Number of received runt packets

RO

0x2B7

Reserved

0x2B8

CNTR_RX_FCS

Number of received packets with FCS errors. This register maintains a count of the number of pulses on the l<n>_rx_fcs_error output signal in variations with a custom streaming client interface (variations without adapters).

RO

Related Information
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