1

Input

This clock is equal to the TX data rate divided by 132. Generated from the same PLL as txframe_clk.

1

Input

Generated from the same PLL as txlink_clk and txframe_clk. This clock acts as a phase information for txlink_clk to handle CDC between txlink_clk and txframe_clk.

1

Input

Synchronous with txlink_clk. Frequency is equal, 2x, or 4x txlink_clk, based on the selected option for the frame clock frequency multiplier parameter. Generated from the same PLL as txlink_clk. .

1

Input

Generated from the same PLL as txlink_clk and txframe_clk. This clock acts as a phase information for txframe_clk to handle CDC between txlink_clk and txframe_clk.

1

Input

Avalon® memory-mapped interface clock.

Input

Transceiver reconfiguration clock. In duplex mode, both TX and RX share the same reconfig pins.

1

Input

Active-low asynchronous reset signal for MAC LL and TL.

Input

Active-low asynchronous reset signal for PHY.

Input

Active-low asynchronous reset signal for TX Avalon® memory-mapped interface.

Input

Active-high reset signal for transceiver reconfiguration. In duplex mode, both TX and RX share the same reconfig pins.

L

Output

Differential high speed serial output data. The clock is embedded in the serial data stream.

L

Output

Differential high speed serial output data. The clock is embedded in the serial data stream.

1

Input

When this signal is present, the slave port ignores all Avalon® memory-mapped signals unless this signal is asserted. This signal must be used in combination with read or write. If the Avalon® memory-mapped bus does not support chip select, you are recommended to tie this port to 1.

10

Input

For Avalon® memory-mapped slave, each slave access is based on byte-based offset. For example, address = 0 selects the first four bytes of the slave register and the address = 4 selects the next four bytes of the slave register space.

32

Input

32-bit data for write transfers. The width of this signal and the j204c_tx_avs_readdata[31:0] signal must be the same if both signals are present.

1

Input

This signal is asserted to indicate a read transfer. This is an active high signal and requires the j204c_tx_avs_readdata[31:0] signal to be in use.

1

Input

This signal is asserted to indicate a write transfer. This is an active high signal and requires the j204c_tx_avs_writedata[31:0] signal to be in use.

32

Output

32-bit data driven from the Avalon® memory-mapped slave to master in response to a read transfer.

1

Output

This signal is asserted by the Avalon® memory-mapped slave to indicate that it is unable to respond to a read or write request. The JESD204C Intel® FPGA IP ties this signal to 0 to return the data in the access cycle.

M*S*WIDTH_MULP*N

Input

The minimum data width = M*S*N. Indicates the converter samples that will be processed by TL.

The data format is big endian.

If L=1 and M*S*WIDTH_MULP*N=128, the first octet is located at bit[127:120], second octet at bit[119:112], and the last octet at bit[7:0].

If more than one lane is instantiated, lane 0 data is always located in the upper M*S*WIDTH_MULP*N bit data lane, followed by the next lane, with the first octet position for lane 0 is at MSB.

Input

Control bits to be inserted as part of CS parameter.

1

Input

Indicates whether the data from the application layer is valid or invalid. The Avalon® streaming sink interface in the TX core cannot be backpressured and assumes that the data is always valid on every cycle when the j204c_tx_avst_ready signal is asserted.

• 0—data is invalid
• 1—data is valid

1

Output

Indicates that the Avalon® streaming sink interface in the TX core is ready to accept data. The Avalon® streaming sink interface asserts this signal on the JESD204C transport state of USER_DATA phase. The ready latency is 0.

1

Output

Indicates that the link layer is ready to accept data. The link layer asserts this signal on a predetermined time before the assertion of the j204c_tx_avst_ready signal.

L*n

Input

Indicates a 6/18-bit user command (per lane) at txlink_clk clock rate. The data format is big endian.

If more than one lane is instantiated, lane 0 data is always located at the upper 18 bits or 6 bits of data. Lane L is located at bit[17:0] or bit[5:0], with the first command bit position for lane L at bit[17] or bit[5].

1

Input

Indicates whether the command from the application layer is valid or invalid. The Avalon® streaming sink interface in the TX core cannot be backpressured and assumes that data is always valid on every cycle when the j204c_tx_cmd_ready signal is asserted.

• 0—data is invalid
• 1—data is valid

1

Output

Indicates that the Avalon® streaming sink interface in the TX core is ready to accept command. The Avalon® streaming sink interface asserts this signal on the JESD204C link/transport state of USER_DATA phase. The ready latency is 0.

1

Input

SYSREF signal for JESD204C Subclass 1 implementation.

For Subclass 0 mode, tie-off this signal to 0.

1

Output

Start of multiblock.

1

Output

Start of extended multiblock.

4

Output

Indicates the number of active lanes for the link. The transport layer can use this signal as a compile-time parameter.

8

Output

Indicates the number of octets per frame. The transport layer uses this signal as a compile-time parameter.

8

Output

Indicates the number of converters for the link. The transport layer uses this signal as a compile-time parameter.

2

Output

Indicates the number of control bits per sample. The transport layer uses this signal as a compile-time parameter.

5

Output

Indicates the converter resolution. The transport layer uses this signal as a compile-time parameter.

5

Output

Indicates the total number of bits per sample. The transport layer uses this signal as a compile-time parameter.

5

Output

Indicates the number of samples per converter per frame cycle. The transport layer uses this signal as a compile-time parameter.

1

Output

Indicates the high density data format. The transport layer uses this signal as a compile-time parameter.

5

Output

Indicates the number of control words per frame clock period per link. The transport layer uses this signal as a compile-time parameter.

Output

LEMC period

1

Output

Interrupt pin for the JESD204C Intel® FPGA IP.

Interrupt is asserted when any error or synchronization request is detected. Configure the tx_err_enable register to set the type of error that can trigger an interrupt.

Output

Output as 132-bit width data before the TX gearbox to connect to the RX core (same signal name) for 2-block loopback function.

If L>0, LSB of this bus is mapped to lane 0. MSB is mapped to lane L–1.

1

Input

This clock is equal to the TX data rate divided by 132. Generated from the same PLL as txframe_clk.

1

Input

Generated from the same PLL as txlink_clk and txframe_clk. This clock acts as a phase information for txlink_clk to handle CDC between txlink_clk and txframe_clk.

1

Input

Synchronous with txlink_clk. Frequency is equal, 2x, or 4x txlink_clk, based on the selected option for the frame clock frequency multiplier parameter. Generated from the same PLL as txlink_clk. .

1

Input

Generated from the same PLL as txlink_clk and txframe_clk. This clock acts as a phase information for txframe_clk to handle CDC between txlink_clk and txframe_clk.

1

Input

Avalon® memory-mapped interface clock.

1

Input

This clock is equal to the TX data rate divided by 64. Asynchronous with frame or link clock.

1

Input

Active-low asynchronous reset signal for MAC LL and TL.

Input

Active-low asynchronous reset signal for PHY.

Input

Active-low asynchronous reset signal for TX Avalon® memory-mapped interface.

1

Input

When this signal is present, the slave port ignores all Avalon® memory-mapped signals unless this signal is asserted. This signal must be used in combination with read or write. If the Avalon® memory-mapped bus does not support chip select, you are recommended to tie this port to 1.

10

Input

For Avalon® memory-mapped slave, each slave access is based on byte-based offset. For example, address = 0 selects the first four bytes of the slave register and the address = 4 selects the next four bytes of the slave register space.

32

Input

32-bit data for write transfers. The width of this signal and the j204c_tx_avs_readdata[31:0] signal must be the same if both signals are present.

1

Input

This signal is asserted to indicate a read transfer. This is an active high signal and requires the j204c_tx_avs_readdata[31:0] signal to be in use.

1

Input

This signal is asserted to indicate a write transfer. This is an active high signal and requires the j204c_tx_avs_writedata[31:0] signal to be in use.

32

Output

32-bit data driven from the Avalon® memory-mapped slave to master in response to a read transfer.

1

Output

This signal is asserted by the Avalon® memory-mapped slave to indicate that it is unable to respond to a read or write request. The JESD204C Intel® FPGA IP ties this signal to 0 to return the data in the access cycle.

M*S*WIDTH_MULP*N

Input

The minimum data width = M*S*N. Indicates the converter samples that will be processed by TL.

The data format is big endian.

If L=1 and M*S*WIDTH_MULP*N=128, the first octet is located at bit[127:120], second octet at bit[119:112], and the last octet at bit[7:0].

If more than one lane is instantiated, lane 0 data is always located in the upper M*S*WIDTH_MULP*N bit data lane, followed by the next lane, with the first octet position for lane 0 is at MSB.

Input

Control bits to be inserted as part of CS parameter.

1

Input

Indicates whether the data from the application layer is valid or invalid. The Avalon® streaming sink interface in the TX core cannot be backpressured and assumes that the data is always valid on every cycle when the j204c_tx_avst_ready signal is asserted.

• 0—data is invalid
• 1—data is valid

1

Output

Indicates that the Avalon® streaming sink interface in the TX core is ready to accept data. The Avalon® streaming sink interface asserts this signal on the JESD204C transport state of USER_DATA phase. The ready latency is 0.

1

Output

Indicates that the link layer is ready to accept data. The link layer asserts this signal on a predetermined time before the assertion of the j204c_tx_avst_ready signal.

L*n

Input

Indicates a 6/18-bit user command (per lane) at txlink_clk clock rate. The data format is big endian.

If more than one lane is instantiated, lane 0 data is always located at the upper 18 bits or 6 bits of data. Lane L is located at bit[17:0] or bit[5:0], with the first command bit position for lane L at bit[17] or bit[5].

1

Input

Indicates whether the command from the application layer is valid or invalid. The Avalon® streaming sink interface in the TX core cannot be backpressured and assumes that data is always valid on every cycle when the j204c_tx_cmd_ready signal is asserted.

• 0—data is invalid
• 1—data is valid

1

Output

Indicates that the Avalon® streaming sink interface in the TX core is ready to accept command. The Avalon® streaming sink interface asserts this signal on the JESD204C link/transport state of USER_DATA phase. The ready latency is 0.

1

Input

SYSREF signal for JESD204C Subclass 1 implementation.

For Subclass 0 mode, tie-off this signal to 0.

1

Output

Start of multiblock.

1

Output

Start of extended multiblock.

4

Output

Indicates the number of active lanes for the link. The transport layer can use this signal as a compile-time parameter.

8

Output

Indicates the number of octets per frame. The transport layer uses this signal as a compile-time parameter.

8

Output

Indicates the number of converters for the link. The transport layer uses this signal as a compile-time parameter.

2

Output

Indicates the number of control bits per sample. The transport layer uses this signal as a compile-time parameter.

5

Output

Indicates the converter resolution. The transport layer uses this signal as a compile-time parameter.

5

Output

Indicates the total number of bits per sample. The transport layer uses this signal as a compile-time parameter.

5

Output

Indicates the number of samples per converter per frame cycle. The transport layer uses this signal as a compile-time parameter.

1

Output

Indicates the high density data format. The transport layer uses this signal as a compile-time parameter.

5

Output

Indicates the number of control words per frame clock period per link. The transport layer uses this signal as a compile-time parameter.

Output

LEMC period

1

Output

Interrupt pin for the JESD204C Intel® FPGA IP.

Interrupt is asserted when any error or synchronization request is detected. Configure the tx_err_enable register to set the type of error that can trigger an interrupt.

Output

Output as 132-bit width data before the TX gearbox to connect to the RX core (same signal name) for 2-block loopback function.

If L>0, LSB of this bus is mapped to lane 0. MSB is mapped to lane L–1.