JESD204C Intel® FPGA IP User Guide

Download PDF
ID 683108
Date 6/26/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. About the JESD204C Intel FPGA IP User Guide 2. Overview of the JESD204C Intel FPGA IP 3. Functional Description 4. Getting Started 5. Designing with the JESD204C Intel® FPGA IP 6. JESD204C Intel® FPGA IP Parameters 7. Interface Signals 8. Control and Status Registers 9. JESD204C Intel® FPGA IP User Guide Archives 10. Document Revision History for the JESD204C Intel® FPGA IP User Guide
2. Overview of the JESD204C Intel FPGA IP x
2.1. Release Information 2.2. Device Family Support 2.3. JESD204C Intel® FPGA IP Features 2.4. Presets 2.5. Performance and Resource Utilization
3. Functional Description x
3.1. Clocks 3.2. Local Extended Multiblock Clock 3.3. CRC Encoding/Decoding 3.4. Scrambler/Descrambler
3.1. Clocks x
3.1.1. Device Clock 3.1.2. Frame Clock and Link Clock
3.2. Local Extended Multiblock Clock x
3.2.1. LEMC Counter
4. Getting Started x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Intel® FPGA IP Evaluation Mode 4.3. IP Catalog and Parameter Editor 4.4. JESD204C IP Component Files 4.5. Creating a New Intel® Quartus® Prime Project 4.6. Parameterizing and Generating the IP 4.7. Compiling the JESD204C IP Design 4.8. Programming an FPGA Device
5. Designing with the JESD204C Intel® FPGA IP x
5.1. JESD204C TX and RX Reset Sequence 5.2. Configuration Phase 5.3. Link Reinitialization 5.4. SYSREF Sampling 5.5. Interrupt and Error Handling 5.6. Deterministic Latency
5.5. Interrupt and Error Handling x
5.5.1. Interrupt Configuration for TX and RX 5.5.2. Interrupt Top Half ISR Handler 5.5.3. Interrupt Bottom Half ISR Handler
7. Interface Signals x
7.1. Transmitter Signals 7.2. Receiver Signals
8. Control and Status Registers x
8.1. Transmitter Registers 8.2. Receiver Registers
1. About the JESD204C Intel FPGA IP User Guide
2. Overview of the JESD204C Intel FPGA IP
3. Functional Description
4. Getting Started
5. Designing with the JESD204C Intel® FPGA IP
6. JESD204C Intel® FPGA IP Parameters
7. Interface Signals
8. Control and Status Registers
9. JESD204C Intel® FPGA IP User Guide Archives
10. Document Revision History for the JESD204C Intel® FPGA IP User Guide

3.1.1. Device Clock

In a converter device, the sampling clock is typically the device clock. The JESD204C IP uses the device clock to generate the desired internal clocks for the transceivers and core logic.

For the JESD204C IP link in an FPGA logic device, you can select one of the options provided in the PLL/CDR reference clock frequency parameter in the JESD204C IP parameter editor.

In the single reference clock design, both sets of pins are driven by the same clock source. The device clock is used as the transceiver PLL reference clock and also the core PLL reference clock. In the dual reference clock design, each set of pins are driven by a different clock source. The device clock is used as the core PLL reference clock and the other reference clock (phase-locked to device clock) is used as the transceiver PLL reference clock. If you want to use the same reference clock for the transceiver and core PLLs, you must use two separate input pins for these PLL reference clocks in your design. Use a common clock source on the board to generate two separate clocks of the same frequency to drive the inputs.

The device clock frequency depends on the data rate and total number of lanes. When you generate the IP, the Intel® Quartus® Prime Pro Edition software provides the available reference frequency for the transceiver PLL and core PLL based on your selection.

For Subclass 1 application, ensure that the routing of the SYSREF signal and the device clock to the FPGA has matching trace lengths.

Level Two Title