JESD204C Intel® FPGA IP User Guide

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ID 683108
Date 6/26/2023
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Document Table of Contents
Document Table of Contents x
1. About the JESD204C Intel FPGA IP User Guide 2. Overview of the JESD204C Intel FPGA IP 3. Functional Description 4. Getting Started 5. Designing with the JESD204C Intel® FPGA IP 6. JESD204C Intel® FPGA IP Parameters 7. Interface Signals 8. Control and Status Registers 9. JESD204C Intel® FPGA IP User Guide Archives 10. Document Revision History for the JESD204C Intel® FPGA IP User Guide
2. Overview of the JESD204C Intel FPGA IP x
2.1. Release Information 2.2. Device Family Support 2.3. JESD204C Intel® FPGA IP Features 2.4. Presets 2.5. Performance and Resource Utilization
3. Functional Description x
3.1. Clocks 3.2. Local Extended Multiblock Clock 3.3. CRC Encoding/Decoding 3.4. Scrambler/Descrambler
3.1. Clocks x
3.1.1. Device Clock 3.1.2. Frame Clock and Link Clock
3.2. Local Extended Multiblock Clock x
3.2.1. LEMC Counter
4. Getting Started x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Intel® FPGA IP Evaluation Mode 4.3. IP Catalog and Parameter Editor 4.4. JESD204C IP Component Files 4.5. Creating a New Intel® Quartus® Prime Project 4.6. Parameterizing and Generating the IP 4.7. Compiling the JESD204C IP Design 4.8. Programming an FPGA Device
5. Designing with the JESD204C Intel® FPGA IP x
5.1. JESD204C TX and RX Reset Sequence 5.2. Configuration Phase 5.3. Link Reinitialization 5.4. SYSREF Sampling 5.5. Interrupt and Error Handling 5.6. Deterministic Latency
5.5. Interrupt and Error Handling x
5.5.1. Interrupt Configuration for TX and RX 5.5.2. Interrupt Top Half ISR Handler 5.5.3. Interrupt Bottom Half ISR Handler
7. Interface Signals x
7.1. Transmitter Signals 7.2. Receiver Signals
8. Control and Status Registers x
8.1. Transmitter Registers 8.2. Receiver Registers
1. About the JESD204C Intel FPGA IP User Guide
2. Overview of the JESD204C Intel FPGA IP
3. Functional Description
4. Getting Started
5. Designing with the JESD204C Intel® FPGA IP
6. JESD204C Intel® FPGA IP Parameters
7. Interface Signals
8. Control and Status Registers
9. JESD204C Intel® FPGA IP User Guide Archives
10. Document Revision History for the JESD204C Intel® FPGA IP User Guide

6. JESD204C Intel® FPGA IP Parameters

Table 20.   JESD204C Intel® FPGA IP Parameters
Parameter Value Description
Main Tab
Device family

Intel Agilex® 7

Intel® Stratix® 10 (E-tile)

Supports Intel Agilex® 7 and Intel® Stratix® 10 E-tile devices.
JESD204C wrapper
  • Base Only
  • PHY Only
  • Both Base and PHY
 Select the JESD204C wrapper.
  • Base Only—generates the data link layer and transport layer.
  • PHY Only—generates the transceiver PHY layer only (hard PCS).
  • Both Base and PHY—generates both the base (data link layer and transport layer) and the transceiver PHY layer (hard PCS).
Data path
  • Simplex Receiver
  • Simplex Transmitter
  • Duplex

Select the operation modes. This selection enables or disables the receiver and transmitter supporting logic.

  • Simplex Receiver—instantiates the receiver to interface to the ADC.
  • Simplex Transmitter—instantiates the transmitter to interface to the DAC.
  • Duplex—instantiates the receiver and transmitter to interface to both the ADC and DAC.

JESD204C Subclass

  • 0
  • 1

Select the JESD204C subclass modes.

  • 0—Set subclass 0
  • 1—Set subclass 1

Data rate

5.0–28.9 Gbps

Set the lane rate for each lane. The maximum rate is 28.9 Gbps.

Refer to Performance and Resource Utilization for more information.

Transceiver type

E-tile Default option is E-tile.
Bonding mode
  • Bonded
  • Non-bonded
 Set the bonding modes.
  • Bonded—Select this option to minimize inter-lanes skew for the transmitter datapath.
  • Non-bonded—Select this option to disable inter-lanes skew control for the transmitter datapath.

PLL/CDR reference clock frequency

Variable

Set the transceiver reference clock frequency for PLL or CDR. The frequency range available for you to choose depends on the data rate.

Enable dynamic reconfiguration

On

 This option enables dynamic data rate change.
Enable Native PHY Debug Master Endpoint (NPDME) On, Off This option enables the Transceiver Native PHY IP core to include an embedded Native PHY debug master endpoint. This endpoint connects internally to the Avalon-MM slave interface of the Transceiver Native PHY and can access the reconfiguration space of the transceiver. It can perform certain test and debug functions through JTAG using System Console.
Enable capability registers On, Off This option enables capability registers, which provides high level information about the transceiver channel's configuration.
Set user-defined IP identifier

0–255

 Set a user-defined numeric identifier that can be read from the identifier offset when the capability registers are enabled.
Enable control and status registers On, Off This option enables soft registers for reading status signals and writing control signals on the PHY interface through the embedded debug.
JESD204C Configurations Tab

Lanes per converter device (L)

1–16

Set the number of lanes per converter device.

Converters per device (M)

1–32

Set the number of converters per converter device.

Octets per frame (F)

1–256

The number of octets per frame is derived from F= M*N'*S/(8*L).

Converter resolution (N)

1–32

Set the number of conversion bits per converter.

Transmitted bits per sample (N')

4–32

Set the number of transmitted bits per sample (JESD204 word size, which is in nibble group).

Note: If parameter CF equals to 0 (no control word), parameter N' must be larger than or equal to sum of parameter N and parameter CS (N' ≥ N + CS). Otherwise, parameter N' must be larger than or equal to parameter N (N'≥N).

Samples per converter per frame (S)

1–32

Set the number of transmitted samples per converter per frame.

Multiblocks in an extended multiblock (E)

1–32

Set the number of multiblock within an extended multiblock.

Control bits (CS)

0–3

Set the number of control bits per conversion sample.

Control words (CF)

0–31

Set the number of control words per frame clock period per link.

High-density user data format (HD)

0–1

Turn on this option to set the data format. This parameter controls whether a sample may be divided over more lanes.

  • On: High Density format
  • Off: Data should not cross the lane boundary
Sync header configuration (SH_CONFIG)
  • CRC-12
  • Standalone command channels
 Sets the SH encoding configuration.
  • CRC-12: For the sync word to contain error detection information.
  • Standalone command channel: For the sync word to contain transmit commands and status information.
Frame clock frequency multiplier (FCLK_MULP)

1, 2, 4

Select the frame clock frequency multiplier.

  • 1: Frame clock and link clock are at the same frequency.
  • 2: Frame clock frequency is two times the link clock frequency.
  • 4: Frame clock frequency is four times the link clock frequency.
Note:

When the frame clock frequency multiplier is 2, Intel recommends that you use the following data rates with the stipulated FPGA fabric speed grades if you encounter timing closure difficulties for Intel® Stratix® 10 devices.

  • –1 = up to 21.5 Gbps
  • –2 = up to 19.5 Gbps
  • –3 = up to 17.4 Gbps
Frame data width multiplier (WIDTH_MULP)

1, 2, 4, 8, 16

Select the data width multiplier between the application layer and transport layer.

Note: The multiplier value is auto-calculated based on the M, N, S, and F configurations. Select the smallest data width multiplier value on the list. Other data width multiplier values are not allowed.
Enable TX data pipestage (Transmitter)

0, 1, 2

Select the number of pipeline stages in TX datapath for timing improvement. Setting values of 1 or 2 usually requires additional resources.

  • 0: Do not insert any pipeline stage. Minimum latency.
  • 1: Insert 1 pipeline stage.
  • 2: Insert 2 pipeline stages.
Note: For high data rates, Intel recommends that you insert 2 pipeline stages for better timing.
Use MLAB DCFIFO in TX Gearbox (Transmitter)

On, Off

Select the type of FIFO used in the TX gearbox. By default, the gearbox uses M20K FIFO. Enable this parameter to use MLAB FIFO.

TX LEMC offset (Transmitter)

0–255

TX LEMC offset from SYSREF. Default is 0.

EMB error threshold (Receiver)

1–8

EMB error threshold to unlock EMB FSM back to initialization state. Default is 8.

SH error threshold (Receiver)

1–16

 Sync header error threshold to unlock SH FSM back to initialization state. Default is 16.
RX LEMC offset (Receiver)

0–255

RX LEMC offset from SYSREF. Default is 0.

RBD offset (Receiver)

0–511

Elastic buffer released point (reference to LEMC) for Subclass 1 usage. Default is 0.

One full LEMC, N number means (LEMC – N) cycles to release data in elastic buffer when deskew alignment is achieved.

Enable RX data pipestage (Receiver)

On, Off

Turn on to add pipeline stage in RX datapath for timing improvement. Enabling this option usually requires additional resources.

Use MLAB DCFIFO in RX gearbox (Receiver)

On, Off

Select the type of FIFO used in the RX gearbox. By default, gearbox uses M20K FIFO. Enable this parameter to use MLAB FIFO to achieve better timing and performance.

Enable ECC in M20K DCFIFO (Receiver)

On, Off

Turn on to enable ECC feature if M20K is used as FIFO.
Lane polarity attribute
  • Optimize away
  • Writable

Select whether you want the lane polarity attribute to be read-only (RO) or read and write (RW).

  • Optimize away: Select this option to enable the attribute to be read-only.
  • Writable: Select this option to enable the attribute to be read and write.

Applies only for RX.
Enable lane polarity detection (Receiver)

16'h0–16'hFFFF

Specify the bit representing the polarity enable status of each lane. For example, LSB represents lane 0, LSB+1 represents lane 1, MSB represents lane 15, and so on.

This value depends on the number of lanes you specify.

Polarity inversion (Receiver) 16'h0–16'hFFFF

Specify the bit representing the polarity inversion status of each lane. For example, LSB represents lane 0, LSB+1 represents lane 1, MSB represents lane 15, and so on.

This value depends on the number of lanes you specify.

Single lane mode (Receiver)

On, Off

Turn on only when you set the Sync header configuration parameter to Standalone command channel.

Multilink mode (Receiver)

On, Off

Turn on this parameter when you want to implement synchronization between multiple JESD204C RX IP instances. When you turn on this parameter, the j204c_rx_dev_emblock_align and j204c_rx_alldev_emblock_align signals are present.

The IP uses the j204c_rx_dev_emblock_align and j204c_rx_alldev_emblock_align signals together with the j204c_rx_dev_lane_align and j204c_rx_alldev_lane_align signals to achieve multidevice synchronization.

Refer to Receiver Signals for more information about these signals.

Configurations and Status Registers Tab

CSR optimization

On, Off

Turn on to optimize the usage of the registers, including the Avalon-MM interfaces.

Note: For more information about the PMA Adaptation parameters, refer to the PMA Adaptation section in the E-tile Transceiver PHY User Guide.
Related Information
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