1

Input

Transceiver reference clock signal.

1

Input

This clock is equal to the RX data rate divided by 132. Generated from the same PLL as rxframe_clk.

Generated from the same PLL as rxlink_clk and rxframe_clk. This clock acts as a phase information for rxlink_clk to handle CDC between rxlink_clk and rxframe_clk.

1

Input

Synchronous with rxlink_clk. Frequency is equal, 2x, or 4x rxlink_clk. Generated from the same PLL as rxlink_clk.

1

Input

Generated from the same PLL as rxlink_clk and rxframe_clk. This clock acts as a phase information for rxframe_clk to handle CDC between rxlink_clk and rxframe_clk.

1

Input

Avalon® memory-mapped interface clock.

1

Input

Transceiver reconfiguration clock. During duplex mode, both TX and RX share the same reconfig pins.

1

Input

Active-low asynchronous reset signal for MAC LL and TL.

Input

Active-low asynchronous reset signal for PHY.

Input

Active-low asynchronous reset signal for RX Avalon® memory-mapped interface.

Input

Active-high reset signal for transceiver reconfiguration.

During duplex mode, both TX and RX share the same reconfig pins.

L

Input

Differential high speed serial input data. The clock is recovered from the serial data stream.

L

Input

Differential high speed serial input data. The clock is recovered from the serial data stream.

You do not need to connect this signal at the top-level pinout for proper compilation.

L

Output

Indicates that the transceiver RX (per lane) is ready.

L

Output

Indicates that the transceiver RX PMA (per lane) is ready.

1

Input

During duplex mode, both TX and RX share the same reconfig pins.

1

Input

During duplex mode, both TX and RX share the same reconfig pins.

ceil (log2(L)) +19

Input

During duplex mode, both TX and RX share the same reconfig pins.

The lower 19 bits specify the address, the upper bits (log2(L)) specify the channel. If L=1, total address bit is always 19 bits.

8

Output

During duplex mode, both TX and RX share the same reconfig pins.

8

Input

During duplex mode, both TX and RX share the same reconfig pins.

j204c_reconfig_waitrequest

1

Output

Wait request signal.

During duplex mode, both TX and RX share the same reconfig pins.

1

Input

When this signal is present, the slave port ignores all Avalon® memory-mapped signals unless this signal is asserted. This signal must be used in combination with read or write. If the Avalon® memory-mapped bus does not support chip select, you are recommended to tie this port to 1.

10

Input

For Avalon® memory-mapped slave, each slave access is based on byte-based offset. For example, address = 0 selects the first four bytes of the slave register and the address = 4 selects the next four bytes of the slave register space.

32

Input

32-bit data for write transfers.

1

Input

This signal is asserted to indicate a read transfer. This is an active high signal and requires the j204c_rx_avs_readdata[31:0] signal to be in use.

1

Input

This signal is asserted to indicate a write transfer. This is an active high signal and requires the j204c_rx_avs_writedata[31:0] signal to be in use.

32

Output

32-bit data driven from the Avalon® memory-mapped slave to master in response to a read transfer.

1

Output

This signal is asserted by the Avalon® memory-mapped slave to indicate that it is unable to respond to a read or write request. The JESD204C Intel® FPGA IP ties this signal to 0 to return the data in the access cycle.

M*S*WIDTH_MULP*N

Output

The minimum data width = M*S*N. Indicates the converter samples that will be processed by TL.

The data format is big endian.

If L=1 and M*S*WIDTH_MULP*N=128, the first octet is located at bit[127:120], second octet at bit[119:112], and the last octet at bit[7:0].

If more than one lane is instantiated, lane 0 data is always located in the upper and M*S*WIDTH_MULP*N bit data lane, followed by the next lane, with the first octet position for lane 0 is at MSB.

M*S*WIDTH_MULP*CS

Output

Control bits that were inserted as part of CS parameter.

1

Output

Indicates whether the data to the application layer is valid or invalid. The Avalon® streaming sink interface in the RX core cannot be backpressured and assumes that the data is always valid on every cycle when the j204c_rx_avst_ready signal is asserted.

• 0—data is invalid
• 1—data is valid

1

Input

Indicates that the Avalon® streaming sink interface in the application layer is ready to accept data. The Avalon® streaming sink interface asserts this signal on the JESD204C transport state of USER_DATA phase. The ready latency is 0.

L

Output

Indicates when CRC error is detected on previous multiblock.

L*n

Output

Indicates a 6/18-bit user command (per lane) at rxlink_clk clock rate. The data format is big endian.

If more than one lane is instantiated, lane 0 data is always located at the upper 18 bits or 6 bits of data. Lane L is located at bit[17:0] or bit[5:0], with the first command bit position for lane L at bit[17] or bit[5].

1

Output

Indicates whether the command from the link layer is valid or invalid when the j204c_rx_cmd_ready signal is asserted.

• 0—data is invalid
• 1—data is valid

1

Input

Indicates that the transport or application layer is ready to accept command. The application layer interface asserts this signal on the JESD204C link/transport state of USER_DATA phase. The ready latency is 0.

L or 1

Output

Indicates when parity error is detected.

• Width is 1 if you enable single lane mode.
• Width is L if you disable single lane mode.

1

Input

SYSREF signal for JESD204C Subclass 1 implementation.

For Subclass 0 mode, tie-off this signal to 0.

1

Output

Indicates the start of multiblock.

1

Output

Indicates the start of extended multiblock.

1

Output

Indicates sync header lock.

1

Output

Indicates EMB lock.

Output

Indicates that all EMB blocks of all the lanes in a JESD204C IP instance are aligned.

1

Output

Indicates that all lanes in a JESD204C IP instance are aligned.

Input

For multilink synchronization, input the j204c_rx_dev_emblock_align signals from all the JESD204C IP instances to an AND gate and connect the AND gate output to this signal.

1

Input

For multilink synchronization, input the j204c_rx_dev_lane_align signals from all the JESD204C IP instances to an AND gate and connect the AND gate output to this signal.

For single device, connect the j204c_rx_dev_lane_align signal back to this signal.

4

Output

Indicates the number of active lanes for the link. The transport layer uses this signal as a compile-time parameter.

8

Output

Indicates the number of octets per frame. The transport layer uses this signal as a compile-time parameter.

8

Output

Indicates the number of converters for the link. The transport layer uses this signal as a compile-time parameter.

2

Output

Indicates the number of control bits per sample. The transport layer uses this signal as a compile-time parameter.

5

Output

Indicates the converter resolution. The transport layer uses this signal as a compile-time parameter.

5

Output

Indicates the total number of bits per sample. The transport layer uses this signal as a compile-time parameter.

5

Output

Indicates the number of samples per converter per frame cycle. The transport layer uses this signal as a compile-time parameter.

1

Output

Indicates the high density data format. The transport layer uses this signal as a compile-time parameter.

5

Output

Indicates the number of control words per frame clock period per link. The transport layer uses this signal as a compile-time parameter.

Output

LEMC period. The transport layer uses this signal as a compile-time parameter.

4

Output

0000: No test mode.

00x1: Descrambler disabled.

001x: 2-block loopback mode enabled.

Other values are reserved.

1

Output

Interrupt pin for the JESD204C Intel® FPGA IP.

Interrupt is asserted when any error is detected. Configure the rx_err_enable register to set the type of error that can trigger an interrupt.

Input

Multiplexed with the RX gearbox output when 2-block loopback mode is enabled through bit-10 rx_2b_lben (offset 0x0) to connect to the TX core in the duplex setup (same signal name).

If L>0, LSB of this bus is mapped to lane 0. MSB is mapped to lane L-1.

This signal only exists in simplex mode. When the IP is configured as duplex, the parallel loopback path is connected from TX to RX internally.

1

Input

This clock is equal to the RX data rate divided by 132. Generated from the same PLL as rxframe_clk.

Generated from the same PLL as rxlink_clk and rxframe_clk. This clock acts as a phase information for rxlink_clk to handle CDC between rxlink_clk and rxframe_clk.

1

Input

Synchronous with rxlink_clk. Frequency is equal, 2x, or 4x rxlink_clk. Generated from the same PLL as rxlink_clk.

1

Input

Generated from the same PLL as rxlink_clk and rxframe_clk. This clock acts as a phase information for rxframe_clk to handle CDC between rxlink_clk and rxframe_clk.

1

Input

Avalon® memory-mapped interface clock.

1

Input

Active-low asynchronous reset signal for MAC LL and TL.

Input

Active-low asynchronous reset signal for PHY.

Input

Active-low asynchronous reset signal for RX Avalon® memory-mapped interface.

1

Input

When this signal is present, the slave port ignores all Avalon® memory-mapped signals unless this signal is asserted. This signal must be used in combination with read or write. If the Avalon® memory-mapped bus does not support chip select, you are recommended to tie this port to 1.

10

Input

For Avalon® memory-mapped slave, each slave access is based on byte-based offset. For example, address = 0 selects the first four bytes of the slave register and the address = 4 selects the next four bytes of the slave register space.

32

Input

32-bit data for write transfers.

1

Input

This signal is asserted to indicate a read transfer. This is an active high signal and requires the j204c_rx_avs_readdata[31:0] signal to be in use.

1

Input

This signal is asserted to indicate a write transfer. This is an active high signal and requires the j204c_rx_avs_writedata[31:0] signal to be in use.

32

Output

32-bit data driven from the Avalon® memory-mapped slave to master in response to a read transfer.

1

Output

This signal is asserted by the Avalon® memory-mapped slave to indicate that it is unable to respond to a read or write request. The JESD204C Intel® FPGA IP ties this signal to 0 to return the data in the access cycle.

M*S*WIDTH_MULP*N

Output

The minimum data width = M*S*N. Indicates the converter samples that will be processed by TL.

The data format is big endian.

If L=1 and M*S*WIDTH_MULP*N=128, the first octet is located at bit[127:120], second octet at bit[119:112], and the last octet at bit[7:0].

If more than one lane is instantiated, lane 0 data is always located in the upper and M*S*WIDTH_MULP*N bit data lane, followed by the next lane, with the first octet position for lane 0 is at MSB.

M*S*WIDTH_MULP*CS

Output

Control bits that were inserted as part of CS parameter.

1

Output

Indicates whether the data to the application layer is valid or invalid. The Avalon® streaming sink interface in the RX core cannot be backpressured and assumes that the data is always valid on every cycle when the j204c_rx_avst_ready signal is asserted.

• 0—data is invalid
• 1—data is valid

1

Input

Indicates that the Avalon® streaming sink interface in the application layer is ready to accept data. The Avalon® streaming sink interface asserts this signal on the JESD204C transport state of USER_DATA phase. The ready latency is 0.

L

Output

Indicates when CRC error is detected on previous multiblock.

L*n

Output

Indicates a 6/18-bit user command (per lane) at rxlink_clk clock rate. The data format is big endian.

If more than one lane is instantiated, lane 0 data is always located at the upper 18 bits or 6 bits of data. Lane L is located at bit[17:0] or bit[5:0], with the first command bit position for lane L at bit[17] or bit[5].

1

Output

Indicates whether the command from the link layer is valid or invalid when the j204c_rx_cmd_ready signal is asserted.

• 0—data is invalid
• 1—data is valid

1

Input

Indicates that the transport or application layer is ready to accept command. The application layer interface asserts this signal on the JESD204C link/transport state of USER_DATA phase. The ready latency is 0.

L or 1

Output

Indicates when parity error is detected.

• Width is 1 if you enable single lane mode.
• Width is L if you disable single lane mode.

1

Input

SYSREF signal for JESD204C Subclass 1 implementation.

For Subclass 0 mode, tie-off this signal to 0.

1

Output

Indicates the start of multiblock.

1

Output

Indicates the start of extended multiblock.

1

Output

Indicates sync header lock.

1

Output

Indicates EMB lock.

1

Output

Indicates that all lanes for this device are aligned.

1

Input

For multidevice synchronization, input the j204c_rx_dev_lane_align signals from all the devices to an AND gate and connect the AND gate output to this signal.

For single device, connect the j204c_rx_dev_lane_align signal back to this signal.

4

Output

Indicates the number of active lanes for the link. The transport layer uses this signal as a compile-time parameter.

8

Output

Indicates the number of octets per frame. The transport layer uses this signal as a compile-time parameter.

8

Output

Indicates the number of converters for the link. The transport layer uses this signal as a compile-time parameter.

2

Output

Indicates the number of control bits per sample. The transport layer uses this signal as a compile-time parameter.

5

Output

Indicates the converter resolution. The transport layer uses this signal as a compile-time parameter.

5

Output

Indicates the total number of bits per sample. The transport layer uses this signal as a compile-time parameter.

5

Output

Indicates the number of samples per converter per frame cycle. The transport layer uses this signal as a compile-time parameter.

1

Output

Indicates the high density data format. The transport layer uses this signal as a compile-time parameter.

5

Output

Indicates the number of control words per frame clock period per link. The transport layer uses this signal as a compile-time parameter.

Output

LEMC period. The transport layer uses this signal as a compile-time parameter.

4

Output

0000: No test mode.

00x1: Descrambler disabled.

001x: 2-block loopback mode enabled.

Other values are reserved.

1

Output

Interrupt pin for the JESD204C Intel® FPGA IP.

Interrupt is asserted when any error is detected. Configure the rx_err_enable register to set the type of error that can trigger an interrupt.

Input

Multiplexed with the RX gearbox output when 2-block loopback mode is enabled through bit-10 rx_2b_lben (offset 0x0) to connect to the TX core in the duplex setup (same signal name).

If L>0, LSB of this bus is mapped to lane 0. MSB is mapped to lane L-1.

This signal only exists in simplex mode. When the IP is configured as duplex, the parallel loopback path is connected from TX to RX internally.