AN 778: Intel® Stratix® 10 L-Tile/H-Tile Transceiver Usage

ID 683086
Date 6/24/2022
Public
Document Table of Contents

3.1.2. PLL Placement for PCIe Hard IP

If the PCIe Hard IP is configured as Gen1/Gen2 capable IP, the fPLL is used as a transmitter PLL.

If the PCIe Hard IP is configured as Gen3 capable IP, then
  • fPLL is used as a transmitter PLL when running at Gen1/Gen2 speeds.
  • ATX PLL is used as a transmitter PLL when running at Gen3 speeds.
Figure 36. PLL Placement for Gen1 and Gen2 x1/ x2/ x4/ x8
Figure 37. PLL Placement for Gen1 and Gen2 x16
Figure 38. PLL Placement for Gen3 x1/x2/x4/x8
Figure 39. PLL Placement for Gen3 x16
TX PLL Guidelines When Using PCIe
  1. The remaining channels of the L-tile are recommended to be driven by ATX PLL if 4 or more channels of PCIe are used at Gen2 or Gen3 speeds. Using ATX PLL to drive these channels helps achieve better performance. Intel® Quartus® Prime issues a critical warning if fPLL is used to drive the remaining channels.
    Table 13.  TX PLL Guidelines When Using PCIe
    PCIE CONFIG Recommended PLL selection for remaining channels
    PCIE GEN 1 (All lane widths) Any PLL
    PCIE GEN 2 (x4,x8,x16) ATX PLL 5
    PCIE GEN 3 (x4,x8,x16) ATX PLL5
  2. When instantiating PIPE interfaces and PCIe Hard IP in the same transceiver tile, be aware of ATX PLL and ATX-fPLL spacing rules. For more details refer to PLL Placement section.
5 Quartus issues a critical warning if FPLL is used instead of ATX PLL.