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1.1. Using Provided HDL Templates
1.2. Instantiating IP Cores in HDL
1.3. Inferring Multipliers and DSP Functions
1.4. Inferring Memory Functions from HDL Code
1.5. Register and Latch Coding Guidelines
1.6. General Coding Guidelines
1.7. Designing with Low-Level Primitives
1.8. Recommended HDL Coding Styles Revision History
1.4.1.1. Use Synchronous Memory Blocks
1.4.1.2. Avoid Unsupported Reset and Control Conditions
1.4.1.3. Check Read-During-Write Behavior
1.4.1.4. Controlling RAM Inference and Implementation
1.4.1.5. Single-Clock Synchronous RAM with Old Data Read-During-Write Behavior
1.4.1.6. Single-Clock Synchronous RAM with New Data Read-During-Write Behavior
1.4.1.7. Simple Dual-Port, Dual-Clock Synchronous RAM
1.4.1.8. True Dual-Port Synchronous RAM
1.4.1.9. Mixed-Width Dual-Port RAM
1.4.1.10. RAM with Byte-Enable Signals
1.4.1.11. Specifying Initial Memory Contents at Power-Up
1.6.6.1. If Performance is Important, Optimize for Speed
1.6.6.2. Use Separate CRC Blocks Instead of Cascaded Stages
1.6.6.3. Use Separate CRC Blocks Instead of Allowing Blocks to Merge
1.6.6.4. Take Advantage of Latency if Available
1.6.6.5. Save Power by Disabling CRC Blocks When Not in Use
1.6.6.6. Initialize the Device with the Synchronous Load (sload) Signal
3.1. Metastability Analysis in the Intel® Quartus® Prime Software
3.2. Metastability and MTBF Reporting
3.3. MTBF Optimization
3.4. Reducing Metastability Effects
3.5. Scripting Support
3.6. Managing Metastability
3.7. Managing Metastability with the Intel® Quartus® Prime Software Revision History
3.8. Intel® Quartus® Prime Pro Edition User Guide: Design Recommendations Archive
3.4.1. Apply Complete System-Centric Timing Constraints for the Timing Analyzer
3.4.2. Force the Identification of Synchronization Registers
3.4.3. Set the Synchronizer Data Toggle Rate
3.4.4. Optimize Metastability During Fitting
3.4.5. Increase the Length of Synchronizers to Protect and Optimize
3.4.6. Increase the Number of Stages Used in Synchronizers
3.4.7. Select a Faster Speed Grade Device
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1.6.4.3.1. VHDL State Machine Coding Example
The following state machine has five states. The asynchronous reset sets the variable state to state_0.
The sum of in1 and in2 is an output of the state machine in state_1 and state_2. The difference (in1 - in2) is also used in state_1 and state_2. The temporary variables tmp_out_0 and tmp_out_1 store the sum and the difference of in1 and in2. Using these temporary variables in the various states of the state machine ensures proper resource sharing between the mutually exclusive states.
VHDL State Machine
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY vhdl_fsm IS
PORT(
clk: IN STD_LOGIC;
reset: IN STD_LOGIC;
in1: IN UNSIGNED(4 downto 0);
in2: IN UNSIGNED(4 downto 0);
out_1: OUT UNSIGNED(4 downto 0)
);
END vhdl_fsm;
ARCHITECTURE rtl OF vhdl_fsm IS
TYPE Tstate IS (state_0, state_1, state_2, state_3, state_4);
SIGNAL state: Tstate;
SIGNAL next_state: Tstate;
BEGIN
PROCESS(clk, reset)
BEGIN
IF reset = '1' THEN
state <=state_0;
ELSIF rising_edge(clk) THEN
state <= next_state;
END IF;
END PROCESS;
PROCESS (state, in1, in2)
VARIABLE tmp_out_0: UNSIGNED (4 downto 0);
VARIABLE tmp_out_1: UNSIGNED (4 downto 0);
BEGIN
tmp_out_0 := in1 + in2;
tmp_out_1 := in1 - in2;
CASE state IS
WHEN state_0 =>
out_1 <= in1;
next_state <= state_1;
WHEN state_1 =>
IF (in1 < in2) then
next_state <= state_2;
out_1 <= tmp_out_0;
ELSE
next_state <= state_3;
out_1 <= tmp_out_1;
END IF;
WHEN state_2 =>
IF (in1 < "0100") then
out_1 <= tmp_out_0;
ELSE
out_1 <= tmp_out_1;
END IF;
next_state <= state_3;
WHEN state_3 =>
out_1 <= "11111";
next_state <= state_4;
WHEN state_4 =>
out_1 <= in2;
next_state <= state_0;
WHEN OTHERS =>
out_1 <= "00000";
next_state <= state_0;
END CASE;
END PROCESS;
END rtl;