AN 905: JESD204B Intel® FPGA IP and ADI AD9213 Interoperability Report for Intel Stratix® 10 Devices

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ID 683056
Date 12/16/2019
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Document Table of Contents
Document Table of Contents x
1. JESD204B Intel® FPGA IP and ADI AD9213 Interoperability Report for Intel® Stratix® 10 Devices
1. JESD204B Intel® FPGA IP and ADI AD9213 Interoperability Report for Intel® Stratix® 10 Devices x
1.1. Hardware Requirements 1.2. Hardware Setup 1.3. Hardware Checkout Methodology 1.4. JESD204B Intel® FPGA IP and ADC Configurations 1.5. Test Results 1.6. Test Result Comments 1.7. Document Revision History for AN 905: JESD204B Intel® FPGA IP and ADI AD9213 Interoperability Report for Intel® Stratix® 10 Devices 1.8. Appendix
1.3. Hardware Checkout Methodology x
1.3.1. Receiver Data Link Layer 1.3.2. Receiver Transport Layer 1.3.3. Descrambling
1.3.1. Receiver Data Link Layer x
1.3.1.1. Code Group Synchronization 1.3.1.2. Initial Frame and Lane Synchronization
1. JESD204B Intel® FPGA IP and ADI AD9213 Interoperability Report for Intel® Stratix® 10 Devices

1.3.2. Receiver Transport Layer

To check the data integrity of the payload data stream through the JESD204B Intel® FPGA IP core receiver and transport layer, the ADC is configured to output PRBS-9 data pattern. The ADC is also set to operate with the same configuration as set in the JESD204B Intel® FPGA IP core. The PRBS checker/Ramp checker in the FPGA fabric checks data integrity for one minute.

This figure shows the conceptual test setup for data integrity checking.

Figure 3. Data Integrity Check Using PRBS/Ramp Checker
Table 3.  Transport Layer Test Cases
Test Case Objective Description Passing Criteria

TL.1

 Check the transport layer mapping using Ramp test pattern.

The following signals in altera_jesd204_transport_rx_top.sv are tapped:

  • jesd204_rx_data_valid

The following signals in jesd204b_ed.sv are tapped:

  • data_error
  • jesd204_rx_int

The rxframe_clk is used as the sampling clock for the Signal Tap.

The data_error signal indicates a pass or fail for the PRBS checker.

  • The jesd204_rx_data_valid signal is asserted.
  • The data_error and jesd204_rx_int signals are deasserted.

TL.2

 Check the transport layer mapping using PRBS-9 test pattern.

The following signals in altera_jesd204_transport_rx_top.sv are tapped:

  • jesd204_rx_data_valid

The following signals in jesd204b_ed.sv are tapped:

  • data_error
  • jesd204_rx_int

The rxframe_clk is used as the sampling clock for the Signal Tap.

The data_error signal indicates a pass or fail for the PRBS checker.

  • The jesd204_rx_data_valid signal is asserted.
  • The data_error and jesd204_rx_int signals are deasserted.
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