AN 905: JESD204B Intel® FPGA IP and ADI AD9213 Interoperability Report for Intel Stratix® 10 Devices

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ID 683056
Date 12/16/2019
Public
Document Table of Contents
Document Table of Contents x
1. JESD204B Intel® FPGA IP and ADI AD9213 Interoperability Report for Intel® Stratix® 10 Devices
1. JESD204B Intel® FPGA IP and ADI AD9213 Interoperability Report for Intel® Stratix® 10 Devices x
1.1. Hardware Requirements 1.2. Hardware Setup 1.3. Hardware Checkout Methodology 1.4. JESD204B Intel® FPGA IP and ADC Configurations 1.5. Test Results 1.6. Test Result Comments 1.7. Document Revision History for AN 905: JESD204B Intel® FPGA IP and ADI AD9213 Interoperability Report for Intel® Stratix® 10 Devices 1.8. Appendix
1.3. Hardware Checkout Methodology x
1.3.1. Receiver Data Link Layer 1.3.2. Receiver Transport Layer 1.3.3. Descrambling
1.3.1. Receiver Data Link Layer x
1.3.1.1. Code Group Synchronization 1.3.1.2. Initial Frame and Lane Synchronization
1. JESD204B Intel® FPGA IP and ADI AD9213 Interoperability Report for Intel® Stratix® 10 Devices

1.2. Hardware Setup

An Intel® Stratix® 10 GX Signal Integrity Development Kit is used with the ADI AD9213 daughter card module installed to the development board’s FMC+ connector.

  • The AD9213 EVM derives power from the FMC+ pins.
  • The FPGA clock is supplied by a Silicon Labs Si5341 clock generator on the development kit.
  • The Si5341 clock generator provides a reference clock to the ADF4355 clock source. Sampling clock to the ADC AD9213 EVM is given by external clock source ADF 4355.
  • For subclass 1, the FPGA generates SYSREF for the JESD204B Intel® FPGA IP as well as the AD9213 device.
  • SYSREF is provided to ADC through SMA connector.
Figure 1. Hardware Setup
Figure 2. System DiagramThis system-level diagram shows how the different modules connect.

In this setup, where LMF = 812, the data rate of the transceiver lanes is 16 Gbps. An external clock source card provides 400 MHz clock to the FPGA and 6400 MHz sampling clock to AD9213 device. A periodic SYSREF is generated by the FPGA and provided to the ADC through the SMA connector. The JESD204B Intel® FPGA IP core is instantiated in duplex mode but only the receiver path is used.

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