AN 905: JESD204B Intel® FPGA IP and ADI AD9213 Interoperability Report for Intel Stratix® 10 Devices

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ID 683056
Date 12/16/2019
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Document Table of Contents
Document Table of Contents x
1. JESD204B Intel® FPGA IP and ADI AD9213 Interoperability Report for Intel® Stratix® 10 Devices
1. JESD204B Intel® FPGA IP and ADI AD9213 Interoperability Report for Intel® Stratix® 10 Devices x
1.1. Hardware Requirements 1.2. Hardware Setup 1.3. Hardware Checkout Methodology 1.4. JESD204B Intel® FPGA IP and ADC Configurations 1.5. Test Results 1.6. Test Result Comments 1.7. Document Revision History for AN 905: JESD204B Intel® FPGA IP and ADI AD9213 Interoperability Report for Intel® Stratix® 10 Devices 1.8. Appendix
1.3. Hardware Checkout Methodology x
1.3.1. Receiver Data Link Layer 1.3.2. Receiver Transport Layer 1.3.3. Descrambling
1.3.1. Receiver Data Link Layer x
1.3.1.1. Code Group Synchronization 1.3.1.2. Initial Frame and Lane Synchronization
1. JESD204B Intel® FPGA IP and ADI AD9213 Interoperability Report for Intel® Stratix® 10 Devices

1.4. JESD204B Intel® FPGA IP and ADC Configurations

The JESD204B Intel® FPGA IP core parameters of the converter AD9213 need to be configured in the registers at address 0x520 to 0x525. The transceiver data rate, sampling clock frequency, and other JESD204B parameters comply with the AD9213 operating modes.

The hardware checkout testing implements the JESD204B Intel® FPGA IP core with the following parameter configuration.

Global setting for all configuration:

  • CS = 0
  • CF = 0
  • Subclass = 1
  • FPGA Management Clock (MHz) = 100
  • PCS Option = Soft PCS
Table 5.  Parameter Configuration
LMF HD S N ADC Sampling Clock (MHz) FPGA Device Clock (MHz) 3 FPGA Link Clock (MHz) 4 FPGA Frame Clock (MHz) 4 Lane Rate (Gbps) DDC Enabled Decimation Factor Data Pattern
112 0 1 16 3200 400 400 400 16 No 4 PRBS-9 Ramp
211 1 1 16 3200 400 400 400 16 No 2 PRBS-9 Ramp
212 0 2 16 3200 400 400 400 16 No 2 PRBS-9 Ramp
411 1 2 16 3200 400 400 400 16 No 1 PRBS-9 Ramp
412 0 4 16 3200 400 400 400 16 No 1 PRBS-9 Ramp
811 1 4 16 6400 400 400 400 16 No 1 PRBS-9 Ramp
812 0 8 16 6400 400 400 400 16 No 1 PRBS-9 Ramp
16 1 1 1 8 16 6400 200 200 200 8 No 1 PRBS-9 Ramp
16 1 2 0 16 16 6400 200 200 200 8 No 1 PRBS-9 Ramp
124 0 1 16 3200 400 400 400 16 Yes 8 PRBS-9 Ramp
222 0 1 16 3200 400 400 400 16 Yes 4 PRBS-9 Ramp
421 1 1 16 3200 400 400 400 16 Yes 2 PRBS-9 Ramp
422 0 2 16 3200 400 400 400 16 Yes 2 PRBS-9 Ramp
821 1 2 16 6400 400 400 400 16 Yes 2 PRBS-9 Ramp
822 0 4 14 6400 400 400 400 16 Yes 2 PRBS-9 Ramp
16 2 1 1 4 16 6400 200 200 200 8 Yes 2 PRBS-9 Ramp
16 2 2 0 8 16 6400 200 200 200 8 Yes 2 PRBS-9 Ramp
3 The device clock is used to clock the transceiver.
4 The frame clock and link clock is derived from the device clock using an internal PLL.
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