AN 905: JESD204B Intel® FPGA IP and ADI AD9213 Interoperability Report for Intel Stratix® 10 Devices

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ID 683056
Date 12/16/2019
Public
Document Table of Contents
Document Table of Contents x
1. JESD204B Intel® FPGA IP and ADI AD9213 Interoperability Report for Intel® Stratix® 10 Devices
1. JESD204B Intel® FPGA IP and ADI AD9213 Interoperability Report for Intel® Stratix® 10 Devices x
1.1. Hardware Requirements 1.2. Hardware Setup 1.3. Hardware Checkout Methodology 1.4. JESD204B Intel® FPGA IP and ADC Configurations 1.5. Test Results 1.6. Test Result Comments 1.7. Document Revision History for AN 905: JESD204B Intel® FPGA IP and ADI AD9213 Interoperability Report for Intel® Stratix® 10 Devices 1.8. Appendix
1.3. Hardware Checkout Methodology x
1.3.1. Receiver Data Link Layer 1.3.2. Receiver Transport Layer 1.3.3. Descrambling
1.3.1. Receiver Data Link Layer x
1.3.1.1. Code Group Synchronization 1.3.1.2. Initial Frame and Lane Synchronization
1. JESD204B Intel® FPGA IP and ADI AD9213 Interoperability Report for Intel® Stratix® 10 Devices

1.3. Hardware Checkout Methodology

This section describes the test objectives, procedures, and passing criteria. The test covers the following areas:

  • Receiver data link layer
  • Receiver transport layer
  • Descrambling
Level Two Title