AN 833: Intel® Stratix 10® GX 16-Lane RX JESD204B-ADC12DJ3200 Interoperability Reference Design

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ID 683049
Date 12/19/2017
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Document Table of Contents x
Intel® Stratix® 10 GX 16-Lane RX JESD204B-ADC12DJ3200 Interoperability Reference Design
Intel® Stratix® 10 GX 16-Lane RX JESD204B-ADC12DJ3200 Interoperability Reference Design x
Reference Design Block Diagram Key Features Submodules in the Top-Level HDL Files Requirements Reference Design Walkthrough Procedures in the main.tcl System Console Script Document Revision History for AN 833: Intel® Stratix® 10 GX 16-Lane RX JESD204B-ADC12DJ3200 Interoperability Reference Design
Requirements x
Hardware Requirements Software Requirements
Reference Design Walkthrough x
Hardware Set Up Running the Reference Design Viewing the Results Rebuilding Design
Running the Reference Design x
Compiling the Project to Include Signal Tap II File Setting Up the TI ADC12DJxx00 GUI Software and Board Configuring the FPGA Checking the Basic Operation Executing the .tcl Code and Initializing the JESD204B Links Checking the Deterministic Latency
Viewing the Results x
Link Up Test Results Short Transport Layer and Ramp Test Mode Test Results Deterministic Latency Test Results
Short Transport Layer and Ramp Test Mode Test Results x
Verifying Short Transport Test Patterns at Receiver Transport Layer Verifying Ramp Pattern at Output Data of DLL to the Input Receiver Transport Layer
Intel® Stratix® 10 GX 16-Lane RX JESD204B-ADC12DJ3200 Interoperability Reference Design

Verifying Short Transport Test Patterns at Receiver Transport Layer

JESD204B block in the ADC12DJ3200 device defines the short transport test pattern for N’=12 test mode to verify that the transport layer test patterns in transmitter and receiver are operating correctly.

To verify the short transport test patterns at the receiver transport layers of the FPGA, follow these steps:

  1. In the Intel® Quartus® Prime Pro Edition software, click Tools > Signal Tap II Logic Analyzer.
  2. Check the JTAG chain configuration. Select the hardware and device correctly.
  3. In the Instance Manager, click rx_tprt > run Analysis/Autorun Analysis.
The output of RX transport layers for both links are grouped in 16 groups in the Signal Tap II waveform. Each group has 60 bits. You may further split the 60-bit buses into 12-bit buses as indicated in the following figure to match with the following table.
Figure 10. Short Transport Test Patterns Captured at the Output of RX Transport Layers

Ensure both link 0 and link 1 of receiver output transport layers are matched with the following table.

Table 3.  Short Transport Test Patterns for N’=12 Modes (Length = 1 Frame)This table is taken from the ADC12DJ3200 datasheet.
Link Octet 0 1 2 3 4 5 6 7
Nibble 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
8 lanes of link 0 DA0 0xF01 0xF02 0xF03 0xF04 0xF05 T
DA1 0xE11 0xE12 0xE13 0xE14 0xE15 T
DA2 0xD21 0xD22 0xD23 0xD24 0xD25 T
DA3 oxC31 oxC32 oxC33 oxC34 oxC35 T
DA4 0xB41 0xB42 0xB43 0xB44 0xB45 T
DA5 0xA51 0xA52 0xA53 0xA54 0xA55 T
DA6 0x961 0x962 0x963 0x964 0x965 T
DA7 0x871 0x872 0x873 0x874 0x875 T
8 lanes of link 1 DB0 0xF01 0xF02 0xF03 0xF04 0xF05 T
DB1 0xE11 0xE12 0xE13 0xE14 0xE15 T
DB2 0xD21 0xD22 0xD23 0xD24 0xD25 T
DB3 oxC31 oxC32 oxC33 oxC34 oxC35 T
DB4 0xB41 0xB42 0xB43 0xB44 0xB45 T
DB5 0xA51 0xA52 0xA53 0xA54 0xA55 T
DB6 0x961 0x962 0x963 0x964 0x965 T
DB7 0x871 0x872 0x873 0x874 0x875 T
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