AN 833: Intel® Stratix 10® GX 16-Lane RX JESD204B-ADC12DJ3200 Interoperability Reference Design

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ID 683049
Date 12/19/2017
Public
Document Table of Contents
Document Table of Contents x
Intel® Stratix® 10 GX 16-Lane RX JESD204B-ADC12DJ3200 Interoperability Reference Design
Intel® Stratix® 10 GX 16-Lane RX JESD204B-ADC12DJ3200 Interoperability Reference Design x
Reference Design Block Diagram Key Features Submodules in the Top-Level HDL Files Requirements Reference Design Walkthrough Procedures in the main.tcl System Console Script Document Revision History for AN 833: Intel® Stratix® 10 GX 16-Lane RX JESD204B-ADC12DJ3200 Interoperability Reference Design
Requirements x
Hardware Requirements Software Requirements
Reference Design Walkthrough x
Hardware Set Up Running the Reference Design Viewing the Results Rebuilding Design
Running the Reference Design x
Compiling the Project to Include Signal Tap II File Setting Up the TI ADC12DJxx00 GUI Software and Board Configuring the FPGA Checking the Basic Operation Executing the .tcl Code and Initializing the JESD204B Links Checking the Deterministic Latency
Viewing the Results x
Link Up Test Results Short Transport Layer and Ramp Test Mode Test Results Deterministic Latency Test Results
Short Transport Layer and Ramp Test Mode Test Results x
Verifying Short Transport Test Patterns at Receiver Transport Layer Verifying Ramp Pattern at Output Data of DLL to the Input Receiver Transport Layer
Intel® Stratix® 10 GX 16-Lane RX JESD204B-ADC12DJ3200 Interoperability Reference Design

Submodules in the Top-Level HDL Files

The top-level HDL files of this reference design instantiate the following submodules:

  • Top level Platform Designer system
    • JESD204B subsystem includes reset sequencer, two ×8-lane RX JESD204B IP cores, transceiver PHY reset controller, and Avalon® Memory-Mapped (Avalon-MM) pipeline bridge.
    • JTAG-to- Avalon® master bridge for the System Console.
    • Link clock and frame clock generated by the core PLL.
    • Serial peripheral interface (SPI) master—Optional component in this design. You can use this component in your custom design if needed.
  • RX transport layers for link 0 and link 1
  • Test pattern checker
    Note: This test pattern checker is an optional module for this design example and is not suitable to test the ramp pattern transmitted from the ADC12DJ3200 device.
  • Deterministic latency measurement
  • Frequency checker
Related Information
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