AN 833: Intel® Stratix 10® GX 16-Lane RX JESD204B-ADC12DJ3200 Interoperability Reference Design

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ID 683049
Date 12/19/2017
Public
Document Table of Contents
Document Table of Contents x
Intel® Stratix® 10 GX 16-Lane RX JESD204B-ADC12DJ3200 Interoperability Reference Design
Intel® Stratix® 10 GX 16-Lane RX JESD204B-ADC12DJ3200 Interoperability Reference Design x
Reference Design Block Diagram Key Features Submodules in the Top-Level HDL Files Requirements Reference Design Walkthrough Procedures in the main.tcl System Console Script Document Revision History for AN 833: Intel® Stratix® 10 GX 16-Lane RX JESD204B-ADC12DJ3200 Interoperability Reference Design
Requirements x
Hardware Requirements Software Requirements
Reference Design Walkthrough x
Hardware Set Up Running the Reference Design Viewing the Results Rebuilding Design
Running the Reference Design x
Compiling the Project to Include Signal Tap II File Setting Up the TI ADC12DJxx00 GUI Software and Board Configuring the FPGA Checking the Basic Operation Executing the .tcl Code and Initializing the JESD204B Links Checking the Deterministic Latency
Viewing the Results x
Link Up Test Results Short Transport Layer and Ramp Test Mode Test Results Deterministic Latency Test Results
Short Transport Layer and Ramp Test Mode Test Results x
Verifying Short Transport Test Patterns at Receiver Transport Layer Verifying Ramp Pattern at Output Data of DLL to the Input Receiver Transport Layer
Intel® Stratix® 10 GX 16-Lane RX JESD204B-ADC12DJ3200 Interoperability Reference Design

Hardware Set Up

Figure 2.  Intel® Stratix® 10 Transceiver Signal Integrity Development Kit and ADC12DJ3200 EVM Set Up
  1. Set the following MSEL DIP switches to the "1" position to enable JTAG Only Mode.
    • SW11: MSEL0 =1
    • SW10: MSEL1 =1
    • SW10: MSEL2=1
  2. Set the SW3-2 to the ON position to disable MAX® V devices in the JTAG chain.
  3. Set the remaining DIP switches to the factory default settings. Refer to the Factory Default Switch Settings table in the Intel® Stratix® 10 GX Transceiver Signal Integrity Development Kit User Guide.
  4. Slot the ADC12DJ3200 EVM module into FMC+ port A on the Intel® Stratix® 10 Transceiver Signal Integrity Development Kit.
    Ensure the board-to-board FMC+ connection is secure.
  5. Connect the micro-USB cable and power adaptor to the Intel® Stratix® 10 Transceiver Signal Integrity Development Kit.
  6. Connect the mini-USB cable and power cable to the ADC12DJ3200 EVM module.
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