Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs Version 2.0.1 Release Notes: For the Intel FPGA Programmable Acceleration Card D5005

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Date 6/14/2021
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Notice Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs Version 2.0.1 Release Notes for the Intel® FPGA PAC D5005
Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs Version 2.0.1 Release Notes for the Intel® FPGA PAC D5005 x
Acceleration Acronym List Minimum Requirements Intel® Acceleration Stack v2.0.1 Reference Table Intel® Acceleration Stack v2.0.1 Features Known Issues for the Intel® Acceleration Stack v2.0.1 Known Issues for the Intel® Acceleration Stack v2.0.1 AFU Design Examples Revision History for the Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs v2.0.1 Release Notes
Notice
Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs Version 2.0.1 Release Notes for the Intel® FPGA PAC D5005

Intel® Acceleration Stack v2.0.1 Features

Table 3.  Features of the Intel® Acceleration Stack v2.0.1
Feature Description
Security Enhancements
  • Intel® MAX® 10 Root-of-Trust Implementation
  • Support for BMC firmware, BMC RTL, FIM, and AFU signing
  • New OPAE security tools:
    • FPGA one-time secure update (fpgaotsu): Upgrades from v2.0 to v2.0.1
    • FPGA secure update (fpgasupdate): Remotely updates bitstreams securely. fpgasupdate replaces fpgaflash.
    • Super-RSU (super-rsu): Supports v2.0.1 package updates (BMC RTL/firmware and FPGA image).
    • PACSign: Enables signing of bitstreams. To use this tool, you must have the capability to generate a public/private key pair and your hardware security module (HSM) must support a Public-Key Cryptography Standards (PKCS)#11 compatible application programming interface (API) to the PACSign tool.
CCI-P Byte Enable Supports programmable byte writes less than 1 cache line in length. Refer to the Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual for more details.
Networking Interface
  • Interface supports 32-bit PCS direct mode (PMA only).
  • 10 GbE MAC AFU is not provided.
  • Pseudo-random bit stream generator (PRBS) AFU provided to test interface.
Sample AFUs Supported

The following unsigned AFU examples are provided with the Intel Acceleration Stack for Intel Xeon CPU with FPGAs:

  • dma_afu_unsigned.gbs
  • streaming_dma_afu_unsigned.gbs
  • hello_afu_unsigned.gbs
  • hello_mem_afu_unsigned.gbs
  • hello_intr_afu_unsigned.gbs
  • nlb_mode_0_unsigned.gbs
  • nlb_mode_0_stp_unsigned.gbs
  • nlb_mode_3_unsigned.gbs
  • byte_enable_afu_unsigned.gbs
  • hssi_prbs_unsigned.gbs
Note: Each *_unsigned.gbs above is prepended with the necessary block0 and block1 headers but there are no hashes in these headers that have been signed with the root and code signing keys. To learn how to securely sign a provided *_unsigned.gbs refer to the Intel® Acceleration Stack Quick Start Guide: Intel FPGA Programmable Acceleration Card D5005 .
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