Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs Version 2.0.1 Release Notes: For the Intel FPGA Programmable Acceleration Card D5005

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ID 683046
Date 6/14/2021
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Notice Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs Version 2.0.1 Release Notes for the Intel® FPGA PAC D5005
Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs Version 2.0.1 Release Notes for the Intel® FPGA PAC D5005 x
Acceleration Acronym List Minimum Requirements Intel® Acceleration Stack v2.0.1 Reference Table Intel® Acceleration Stack v2.0.1 Features Known Issues for the Intel® Acceleration Stack v2.0.1 Known Issues for the Intel® Acceleration Stack v2.0.1 AFU Design Examples Revision History for the Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs v2.0.1 Release Notes
Notice
Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs Version 2.0.1 Release Notes for the Intel® FPGA PAC D5005

Minimum Requirements

The minimum requirements for the Intel FPGA Programmable Acceleration Card D5005 are:
  • Intel® Xeon® Scalable processor
  • A PCI Express* x16 Slot
  • 128 GB of free memory is a requirement only if you are compiling a hardware design
  • Operating System:
    • Red Hat* Enterprise Linux* (RHEL) version 7.6 Kernel 3.10.0-957
  • PACSign tool requires Python 3.0
  • OPAE tools require Python 2.7
  • OpenCL* RTE version 19.2.0.57
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