Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs Version 2.0.1 Release Notes: For the Intel FPGA Programmable Acceleration Card D5005

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Date 6/14/2021
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Notice Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs Version 2.0.1 Release Notes for the Intel® FPGA PAC D5005
Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs Version 2.0.1 Release Notes for the Intel® FPGA PAC D5005 x
Acceleration Acronym List Minimum Requirements Intel® Acceleration Stack v2.0.1 Reference Table Intel® Acceleration Stack v2.0.1 Features Known Issues for the Intel® Acceleration Stack v2.0.1 Known Issues for the Intel® Acceleration Stack v2.0.1 AFU Design Examples Revision History for the Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs v2.0.1 Release Notes
Notice
Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs Version 2.0.1 Release Notes for the Intel® FPGA PAC D5005

Known Issues for the Intel® Acceleration Stack v2.0.1 AFU Design Examples

Table 5.  Known Issues for the Intel® Acceleration Stack v2.0.1 AFU Design Examples
Known Issue Details
The streaming_dma_afu_unsigned.gbs, dma_afu_unsigned.gbs show timing violations that may limit their operation.
  • Workaround: No workaround available.
  • Status: This limitation will be fixed in a future patch of the Intel® Acceleration Stack.
The Intel® Quartus® Prime Pro Edition compilation report for hello_mem__afu_unsigned.gbs displays Fmax and slack times incorrectly.
  • Workaround: To view the correct timing, open the results in the Timing Analyzer tool or in the timing reports found in /output_files/timing_reports for the final timing reports of the design.
  • Status: This limitation will be fixed in a future version of the Intel® Acceleration Stack.
After a partial reconfiguration of a dma_afu_unsigned.gbs or a streaming dma_afu_unsigned.gbs, First Malformed Req is set in the PORT errors output.
  • Workaround: To clear the errors , you must power cycle the Intel® FPGA PAC.
  • Status: This limitation will be fixed in a future version of the Intel® Acceleration Stack.
Running the fpgabist command on nlb_mode_3_unsigned.gbs reports incorrect output.
  • Instead of reporting the output of a throughput test, a default BIST test runs.
  • Workaround: Load the nlb_mode_3_unsigned.gbs bitstream. Complete the steps below to get read, write and read-write combined bandwidth: 
    $ fpgadiag -B -D -F --mode=read --read-vc=vh0 --write-vc=vh0 --multi-cl=4 --begin=1024 --end=1024 --timeout-sec=5 --cont

$ fpgadiag -B -D -F --mode=write --read-vc=vh0 --write-vc=vh0 --multi-cl=4 --begin=1024 --end=1024 --timeout-sec=5 --cont

$ fpgadiag -B -D -F --mode=trput --read-vc=vh0 --write-vc=vh0 --multi-cl=4 --begin=1024 --end=1024 --timeout-sec=5 --cont
  • Status: This limitation will be fixed in a future version of the Intel® Acceleration Stack.
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