Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs Version 2.0.1 Release Notes: For the Intel FPGA Programmable Acceleration Card D5005

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Notice Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs Version 2.0.1 Release Notes for the Intel® FPGA PAC D5005
Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs Version 2.0.1 Release Notes for the Intel® FPGA PAC D5005 x
Acceleration Acronym List Minimum Requirements Intel® Acceleration Stack v2.0.1 Reference Table Intel® Acceleration Stack v2.0.1 Features Known Issues for the Intel® Acceleration Stack v2.0.1 Known Issues for the Intel® Acceleration Stack v2.0.1 AFU Design Examples Revision History for the Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs v2.0.1 Release Notes
Notice
Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs Version 2.0.1 Release Notes for the Intel® FPGA PAC D5005

Known Issues for the Intel® Acceleration Stack v2.0.1

Table 4.  Known Issues for the Intel® Acceleration Stack v2.0.1
Known Issue Details
The Intel® FPGA PAC D5005 may be unable to recover after an AFU fails to load onto the card. This issue can occur if a *.gbs file is not signed with the correct key or if a *.gbs file is corrupted.
  • When the AFU fails to load on the card, you see this error message:
    WARNING ] Update starting. Please do not interrupt.
libopae-c reconf.c:427:fpgaReconfigureSlot() **ERROR** : Failed to reconfigure bitstream: Input/output error
libopae-c reconf.c:455:fpgaReconfigureSlot() **ERROR** : PR IP protocol error detected
Error writing bitstream to FPGA: reconfiguration error
[2019-11-01 18:23:40,172] [ERROR   ] 
Partial Reconfiguration failed
  • Workaround: To recover after loading a corrupted or incorrectly signed AFU onto the Intel® FPGA PAC D5005, power cycle the card.
  • Status: This limitation will be fixed in a future version of the Intel® Acceleration Stack.
fpgabist -i does not check device ID or report errors on incorrect device ID.
  • Workaround: None available.
  • Status: Fix targeted for a future version of the Intel® Acceleration Stack.
Invalid memory read fault may cause FIM to lock.
  • The FIM locks after the AFU sends a memory read to invalid address.
    • When using fpgainfo, this error displays as compStatErr.
    • When using sudo lspci -vvs B:D.F this error displays as TransPend+entry under DevSta.
  • Workaround: Power cycle the card to reinitialize the Intel® FPGA PAC and recover from this issue. Refer to the Knowledge Base entry for more information.
  • Status: Fix targeted for a future version of the Intel® Acceleration Stack.
The Intel® FPGA PAC D5005 may report that a non-fatal error has occurred during boot.

  • This error is not seen if you are using OPAE drivers. If you do not have the OPAE drivers installed, the Intel® FPGA PAC D5005 responds to configuration read requests to functions that do not exist by returning NonFatalErr+ error responses. You can clear and ignore these errors after boot.

  • Workaround: If you are not using the OPAE driver to handle this error, you can clear the relevant errors at boot:
    sudo setpci -s BDF ECAP_AER+0x10.L=0xFFFFFFFF
  • Status: Fix targeted for a future version of the Intel® Acceleration Stack.
QSFP link and activity LEDs do not reflect Ethernet link status.
  • Workaround: None available.
  • Status: Fix targeted for a future version of the board management controller firmware.
PACSign tool requires Python* version 3.x software to be in /usr/bin.
  • Although the PACSign tool requires Python* version 3.x software to be in /usr/bin, installation from a local zip file typically results in the software being installed to /usr/local/bin.
  • Workaround: When installing from source, complete the following commands:
    tar zxvf Python-3….tgz
cd Python-3…
./configure --prefix=/usr
make
sudo make install
    to install the tool in the correct directory. If you have already installed in /usr/local/bin, you can invoke the PACSign command using python3 /usr/local/bin/PACSign.
  • Status: Fix targeted for a future version of the Intel® Acceleration Stack.
When virtual functions (VF) or physical functions (PF) send multiple unaligned read or write requests to the Intel® FPGA PAC D5005 registers, the host reboots.
  • This issue only exists when using Red Hat* Enterprise Linux* (RHEL) version 7.6 Kernel 3.10.0-957.
  • Workaround: None available.
  • Status: This limitation is addressed in newer Linux* kernels. Intel recommends upgrading from the Red Hat* Enterprise Linux* (RHEL) version 7.6 Kernel 3.10.0-957 kernel. No fixes are planned for this version of the kernel.
The Intel® FPGA PAC D5005 does not support optical module cables that require the ResetL pin to be driven high for link up to complete.
  • Workaround: None available.
  • Status: Fix targeted for a future version of the Intel® Acceleration Stack.
The Intel® FPGA PAC D5005 reports a preset QSFP temperature threshold value irrespective of what is specified in the QSFP module data sheet.
  • The Intel® FPGA PAC D5005 reports a QSFP module temperature of 70C for upper-non critical threshold and 90C for upper non-recoverable threshold regardless of what the specified value is for that QSFP module.
  • Workaround: Monitor the QSFP temperature reported by the sensors to ensure the module is not exceeding operating conditions defined in the QSFP module's data sheet.
  • Status: Fix targeted for a future version of the Intel® Acceleration Stack.
fpgainfo bmc may not return QSFP Supply Voltage if your QSFP module does not support supply voltage registers.
  • The Intel® MAX® 10 BMC obtains the QSFP voltage sensor value from the Supply Voltage registers beginning at offset 26, as listed in the Free Side Monitoring Values Table 6-7, of the SFF8636 Specification for Management Interface for 4-Lane Modules and Cables, rev2.10a.
  • Workaround: If your QSFP module does not support this register please disregard the value returned by the Intel® MAX® 10 BMC when using the fpgainfo bmc command.
  • Status: No fix.
If pacd is killed before it recovers from a sensor trip, fpgasupdate or other accesses to the FPGA may fail.
  • Workaround: Resetting the FPGA is the only way to recover from the failure.
  • Status: Fix targeted for a future version of the Intel® Acceleration Stack.
Running the OpenCL* example may give a segmentation fault.
  • Including the parameter default_hugepagesz=1G creates the error.
  • Workaround: Remove the parameter default_hugepagesz=1G.
  • Status: Fix targeted for a future version of the Intel® Acceleration Stack.
A partial reconfiguration (PR) compile using OpenCL* may produce hold time violations in the static regions.
  • Workaround: Recompile using a different seed with the command:
    aoc <kernal_name.cl> -seed=<integer>
    For example: 
    aoc hello_world.cl -seed=5
  • Status: Fix targeted for a future version of the Intel® Acceleration Stack.
PCIe* bandwidth limitation with OpenCL* designs.
  • PCIe* Gen3x16 operates at a lower throughput than expected only with OpenCL* designs.
  • Workaround: None available.
  • Status: Fix targeted for a future version of the Intel® Acceleration Stack.
PACSign tool requires installation of Python* version 3.x through the rpm process.
  • Installation of Python* verison 3.x from source is not accepted by PACSign. PACSign looks for python 3.x in rpm repository.
  • Workaround: You must install Python3 using the following command before installing the Acceleration Stack for Runtime or the Acceleration Stack for Development.
    sudo yum install python3
  • Status: Fix targeted for a future version of the Intel® Acceleration Stack.
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