Ethernet Design Example Components User Guide

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ID 683044
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. Time-of-day Clock 2. Time-of-day Synchronizer 3. Packet Classifier 4. Ethernet Design Example Components User Guide Archives 5. Document Revision History for the Ethernet Design Example Components User Guide
1. Time-of-day Clock x
1.1. Release Information 1.2. Resource Utilization 1.3. Configuring the TOD Clock 1.4. Using the TOD Clock 1.5. Interface Signals 1.6. Configuration Registers
1.1. Release Information x
1.1.1. Pulse Per Second Device Speed Grade Support
1.4. Using the TOD Clock x
1.4.1. Adjusting TOD Drift 1.4.2. Adjusting Offset, Jitter, and Wander 1.4.3. Correcting TOD Offset 1.4.4. IOPLL and TOD Setup for Pulse Per Second (Advanced Accuracy Mode)
1.4.4. IOPLL and TOD Setup for Pulse Per Second (Advanced Accuracy Mode) x
1.4.4.1. IOPLL and TOD Setup using Dynamic Phase Shift Interface 1.4.4.2. IOPLL and TOD Setup using IOPLL Reconfig IP
1.5. Interface Signals x
1.5.1. Avalon Memory-Mapped Signals 1.5.2. Time-of-day Signals 1.5.3. Pulse-Per-Second Signals 1.5.4. Clocking Requirements
2. Time-of-day Synchronizer x
2.1. Release Information 2.2. Resource Utilization 2.3. Configuring the TOD Synchronizer 2.4. Using the TOD Synchronizer 2.5. Interface Signals
2.4. Using the TOD Synchronizer x
2.4.1. Sampling Clock Frequency
3. Packet Classifier x
3.1. Release Information 3.2. Resource Utilization 3.3. Configuring the Packet Classifier 3.4. Interface Signals
3.4. Interface Signals x
3.4.1. Clock and Reset Signals 3.4.2. Avalon® Streaming Interface Signals 3.4.3. Control Signals
1. Time-of-day Clock
2. Time-of-day Synchronizer
3. Packet Classifier
4. Ethernet Design Example Components User Guide Archives
5. Document Revision History for the Ethernet Design Example Components User Guide

1.4.4.2. IOPLL and TOD Setup using IOPLL Reconfig IP

To set up the IOPLL using the IOPLL Reconfig IP and enable pulse-per-second (advanced accuracy mode) on a TOD clock running on 125MHz period clock for Agilex™ 7 devices, follow these steps:
  1. Create an Quartus® Prime project with Agilex™ 7 device selected.
  2. From IP Catalog, select IOPLL Intel® FPGA IP .
  3. In IP Parameter Editor, apply the following settings and generate the IOPLL instance:
    1. Use the same clock source as TOD period_clk to drive IOPLL reference clock. Set Reference Clock Frequency to 125 MHz.
    2. For Output Clocks section, set Number of Clocks to 2.
      1. Outclk0: Generate pps_sampling_clk, set Desired Frequency to 85.33 MHz (pps_sampling_clk = period_clk *256/375). Sampling clock factor of 256/375 is suitable for all supported period_clk frequencies.
      2. Outclk1: Second clock port of the IOPLL must be allocated for iopll_phased_clk. Set Desired Frequency to the TOD period_clk frequency (125 MHz).
    3. Enable Specify VCO frequency and set Desired VCO Frequency to 1375 MHz.
      • Intel recommends you to specify the VCO frequency value as this value is used to determine PLL unit phase shift parameter value of TOD. Otherwise, you can refer to Advanced Parameters tab for auto assigned VCO frequency.
    4. At Dynamic Reconfiguration tab:
      1. Select Enable dynamic reconfiguration of PLL.
      2. In MIF Generation Options, select Create MIF file during IP Generation.
    5. Generate the IP.
  4. From IP Catalog, select IOPLL Reconfig Intel® FPGA IP .
  5. In IP Parameter Editor, apply the following settings and generate the IOPLL Reconfig IP instance:
    1. Under MIF File settings, paste the path of the generated MIF File.
    2. Generate the IP.
  6. From IP Catalog, select Ethernet IEEE 1588 Time of Day Clock Intel® FPGA IP .
  7. In IP Parameter Editor, apply the following settings and generate the TOD Clock instance:
    1. De-select Enable high clock frequency mode.
    2. Set DEFAULT_NSEC_PERIOD to 8.
    3. Set DEFAULT_FNSEC_PERIOD to 0x0.
    4. Set DEFAULT_NSEC_ADJPERIOD to 8.
    5. Set DEFAULT_FNSEC_ADJPERIOD to 0x0.
    6. Select Enable pulse per second interface.
    7. Select Advanced for Accuracy mode.
    8. Enter desired value for Pulse width.
    9. Enter "100" for PLL scan clock frequency. This example uses a 100 MHz clock to feed iopll_scan_clk.
    10. Enter "90" for PLL unit phase shift. This example has set the IOPLL VCO frequency to 1375 MHz, the unit phase shift equals to 1/8 of IOPLL VCO period, thus 90 ps.
    11. Generate the IP.

When using IOPLL Reconfig IP, the dynamic phase shift interface of the TOD IP is mapped to the IOPLL Reconfig IP ports. The following table shows the mapping of the ports.

Table 10.  TOD Dynamic Phase Shift Ports to IOPLL Reconfig IP Ports Mapping
TOD Dynamic Phase Shift Interface IOPLL Reconfig IP Ports
iopll_phase_done ~ mgmt_waitrequest (inverted assignment)
iopll_phase_en mgmt_write
iopll_num_phase_shifts[2:0] mgmt_writedata[2:0]
iopll_updn mgmt_writedata[3]
iopll_cnt_sel[3:0] mgmt_writedata[7:4]

The diagram below illustrates the connection between IOPLL, IOPLL Reconfig IP, and TOD instances. mgmt_address of IOPLL Reconfig IP can be tied to 10'h300 to select Dynamic phase shift reconfiguration operation mode. Note that the diagram does not elaborate all interfaces of the TOD instance.

Figure 2. Example of connection between IOPLL, IOPLL reconfig IP, and TOD's Advanced Accuracy Pulse Per Second Interfaces
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