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Ixiasoft
1.5.3. Pulse-Per-Second Signals
Name | Direction | Width | Description |
---|---|---|---|
The following signals are available when parameter Enable pulse per second interface is enabled. | |||
pps_pulse_per_second | Out | 1 | Pulse generated once in every second, aligned with the second boundary, with pulse width defined by Pulse width parameter. |
The following signals are available when parameter Enable pulse per second interface is enabled and Accuracy mode is Advanced. You must also instantiate IOPLL parameter and select Enable access to dynamic phase shift ports to support these interfaces. Refer to related information for the related user guides. | |||
pps_sampling_clk | Input | 1 | Sampling clock input used to support pps pulse generation with advanced accuracy. Required frequency (MHz): pps_sampling_clk= period_clk x 256/375 |
iopll_scan_clk | Input | 1 | Drive this port with the same clock as IOPLL scan clock source. Please refer to Example of connections between IOPLL Interface and TOD Clock’s Advanced Accuracy Pulse Per Second Interface diagram and Example of connection between IOPLL, IOPLL reconfig IP, and TOD's Advanced Accuracy Pulse Per Second Interfaces diagram for examples of port connection. Supported frequency (MHz): 50 MHz to 100 MHz.
Note: As IOPLL phase shift operation is running on iopll_scan_clk, faster iopll_scan_clk is recommended for faster IOPLL phase shift operation.
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iopll_phased_clk | Input | 1 | Phase shifted version of period_clk from IOPLL. This signal is expected to be fed by second output clock of IOPLL, e.g. outclk1, which runs on period_clk frequency. Refer to iopll_cnt_sel signal description for more details. |
iopll_locked | Input | 1 | PLL lock status signal from IOPLL. |
iopll_phase_en | Output | 1 | Connect this signal to phase_en input port of IOPLL. |
iopll_updn | Output | 5 | Connect this signal to updn input port of IOPLL. |
iopll_cnt_sel | Output | 5 | Connect this signal to cntsel input port of IOPLL. This signal always select second output clock of IOPLL, e.g. outclk1, to be the one being phase shifted. Therefore, iopll_phased_clk signal is expected to connect to the second output clock of IOPLL. |
iopll_num_phase_shifts | Output | 3 | Connect this signal to num_phase_shifts input port of IOPLL. |
iopll_phase_done | Input | 1 | Connect this signal to phase_done output port of IOPLL. |