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Ixiasoft
2.5. Interface Signals
Figure 6. Interface Signals of TOD Synchronizer
Name | Direction | Width | Description |
---|---|---|---|
Clock and Reset Signals | |||
clk_master | In | 1 | Master TOD clock domain. |
reset_master | In | 1 | Synchronous reset signal in the master TOD clock domain. |
clk_slave | In | 1 | Target TOD clock domain. |
reset_slave | In | 1 | Synchronous reset signal in the target TOD clock domain. |
clk_sampling | In | 1 | Sampling clock to measure the transfer latency. Not available for SYNC_MODE = 18. |
Interface Signals | |||
start_tod_sync | In | 1 | Assert this signal to start the synchronization process. Synchronization continues as long as this signal is asserted. |
tod_master_data[] | In | 64 or 96 | Carries the 64-bit or 96-bit time of day from the master TOD clock. The width of this signal is determined by the TOD_MODE parameter |
tod_slave_valid | Out | 1 | When asserted, the signal indicates that the data on the tod_data_slave bus is valid and ready for transfer in the following cycle. This signal stays asserted for only 1 clock cycle. |
tod_slave_data[] | Out | 64 or 96 | Carries the 64-bit or 96-bit time of day for the target TOD clock. This time of day is synchronized to the master TOD clock with an additional one clock cycle because it takes one clock cycle to transfer the time of day to the target TOD clock. The width of this signal is determined by the TOD_MODE parameter. |