Ethernet Design Example Components User Guide

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ID 683044
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. Time-of-day Clock 2. Time-of-day Synchronizer 3. Packet Classifier 4. Ethernet Design Example Components User Guide Archives 5. Document Revision History for the Ethernet Design Example Components User Guide
1. Time-of-day Clock x
1.1. Release Information 1.2. Resource Utilization 1.3. Configuring the TOD Clock 1.4. Using the TOD Clock 1.5. Interface Signals 1.6. Configuration Registers
1.1. Release Information x
1.1.1. Pulse Per Second Device Speed Grade Support
1.4. Using the TOD Clock x
1.4.1. Adjusting TOD Drift 1.4.2. Adjusting Offset, Jitter, and Wander 1.4.3. Correcting TOD Offset 1.4.4. IOPLL and TOD Setup for Pulse Per Second (Advanced Accuracy Mode)
1.4.4. IOPLL and TOD Setup for Pulse Per Second (Advanced Accuracy Mode) x
1.4.4.1. IOPLL and TOD Setup using Dynamic Phase Shift Interface 1.4.4.2. IOPLL and TOD Setup using IOPLL Reconfig IP
1.5. Interface Signals x
1.5.1. Avalon Memory-Mapped Signals 1.5.2. Time-of-day Signals 1.5.3. Pulse-Per-Second Signals 1.5.4. Clocking Requirements
2. Time-of-day Synchronizer x
2.1. Release Information 2.2. Resource Utilization 2.3. Configuring the TOD Synchronizer 2.4. Using the TOD Synchronizer 2.5. Interface Signals
2.4. Using the TOD Synchronizer x
2.4.1. Sampling Clock Frequency
3. Packet Classifier x
3.1. Release Information 3.2. Resource Utilization 3.3. Configuring the Packet Classifier 3.4. Interface Signals
3.4. Interface Signals x
3.4.1. Clock and Reset Signals 3.4.2. Avalon® Streaming Interface Signals 3.4.3. Control Signals
1. Time-of-day Clock
2. Time-of-day Synchronizer
3. Packet Classifier
4. Ethernet Design Example Components User Guide Archives
5. Document Revision History for the Ethernet Design Example Components User Guide

1.4.3. Correcting TOD Offset

You can use the AdjustPeriod and AdjustCount registers to correct TOD offset between master and target TOD. AdjustPeriod register value is used as effective period value when AdjustCount register is a non-zero value. Write to these registers in sequence: AdjustPeriod register, followed by AdjustCount register. Adjustment happens whenever there is a write to the AdjustCount register.

For example, if the target TOD is faster than master TOD by 'a' ns, to correct the TOD offset of 'a' ns by increasing the value of 'a' for a TOD clock running at 125 MHz (Period register value is 0x8 ns):
  • set AdjustPeriod to '8+b' ns
  • set AdjustCount to 'c'
where 'a = b * c' is fulfilled.

By setting a = 16 ns, b = 2 ns, and c = 8, the logic produces TOD with effective period value of 10 ns (slower) in the next 8 clock cycles. After 8 clock cycles, the logic resumes the normal operation where effective period value = 8 ns.

Similarly, if the target TOD is slower than master TOD, to correct negative TOD offset, set AdjustPeriod to '<Period register value> – b'.

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